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NL17SZ126/D PDF预览

NL17SZ126/D

更新时间: 2024-11-05 23:53:51
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其他 - ETC /
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6页 66K
描述
Non-inverting 3-State Buffer

NL17SZ126/D 数据手册

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NL17SZ126  
Non−inverting 3−State  
Buffer  
The NL17SZ126 is a high performance dual noninverting buffer  
operating from a 1.65 V to 5.5 V supply.  
Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V  
PD  
CC  
http://onsemi.com  
Designed for 1.65 V to 5.5 V V Operation  
CC  
Over Voltage Tolerant Inputs and Outputs  
MARKING  
DIAGRAM  
LVTTL Compatible − Interface Capability With 5.0 V TTL Logic  
with V = 3.0 V  
CC  
5
5
LVCMOS Compatible  
M2d  
24 mA Balanced Output Sink and Source Capability  
1
Near Zero Static Supply Current Substantially Reduces System  
SC70−5/SC−88A/SOT−353  
DF SUFFIX  
Power Requirements  
1
CASE 419A  
3−State OE Input is Active HIGH  
Replacement for NC7SZ126  
Chip Complexity = 36 Feet  
d = Date Code  
PIN ASSIGNMENT  
1
2
3
4
5
OE  
IN A  
1
2
3
5
4
V
CC  
OE  
IN A  
GND  
GND  
OUT Y  
V
CC  
FUNCTION TABLE  
A Input  
OE Input  
Y Output  
OUT Y  
H
H
L
L
H
X
L
H
Z
Figure 1. Pinout (Top View)  
X = Don’t Care  
ORDERING INFORMATION  
OE  
IN A  
OUT Y  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
Figure 2. Logic Symbol  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
March, 2004 − Rev. 2  
NL17SZ126/D  

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