Datasheet > NL17SZ126XV5T2G-L22087

NL17SZ126XV5T2G-L22087

更新时间： 2024-09-17 11:01:43

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
7页	114K
描述
Single Non-Inverting Buffer, 3-State

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NL17SZ126

Non-Inverting 3-State

Buffer

The NL17SZ126 is a high performance single noninverting buffer

operating from a 1.65 V to 5.5 V supply.

http://onsemi.com

Features

• Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V

MARKING

DIAGRAM

• Designed for 1.65 V to 5.5 V V Operation

• Over Voltage Tolerant Inputs and Outputs

• LVTTL Compatible − Interface Capability With 5.0 V TTL Logic

with V = 3.0 V

M2 M G

SC−88A (SOT−353)

• LVCMOS Compatible

DF SUFFIX

CASE 419A

• 24 mA Balanced Output Sink and Source Capability

• Near Zero Static Supply Current Substantially Reduces System

Power Requirements

• 3−State OE Input is Active HIGH

• Replacement for NC7SZ126

M2 MG

SOT−553

XV5 SUFFIX

CASE 463B

• Chip Complexity = 36 FETs

• These Devices are Pb−Free and are RoHS Compliant

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

M2 = Specific Device Code

= Date Code

= Pb−Free Package

(Note: Microdot may be in either location)

*Date Code orientation and/or position may vary

depending upon manufacturing location.

PIN ASSIGNMENT

IN A

GND

IN A

GND

OUT Y

FUNCTION TABLE

A Input

OE Input

Y Output

Figure 1. Pinout (Top View)

X = Don’t Care

IN A

OUT Y

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

Figure 2. Logic Symbol

Semiconductor Components Industries, LLC, 2012

Publication Order Number:

May, 2012 − Rev. 10

NL17SZ126/D

12 3 4 5 6 7

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