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NL17SZ126_06 PDF预览

NL17SZ126_06

更新时间: 2024-09-16 03:46:23
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 77K
描述
Non−Inverting 3−State Buffer

NL17SZ126_06 数据手册

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NL17SZ126  
Non−Inverting 3−State  
Buffer  
The NL17SZ126 is a high performance single noninverting buffer  
operating from a 1.65 V to 5.5 V supply.  
http://onsemi.com  
Features  
Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V  
PD  
CC  
MARKING  
DIAGRAM  
Designed for 1.65 V to 5.5 V V Operation  
CC  
Over Voltage Tolerant Inputs and Outputs  
LVTTL Compatible − Interface Capability With 5.0 V TTL Logic  
with V = 3.0 V  
CC  
M2 M G  
G
LVCMOS Compatible  
SC−88A (SOT−353)  
DF SUFFIX  
CASE 419A  
24 mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
3−State OE Input is Active HIGH  
Replacement for NC7SZ126  
Chip Complexity = 36 Feet  
M2 MG  
G
SOT−553  
XV5 SUFFIX  
CASE 463B  
Pb−Free Packages are Available  
M2 = Specific Device Code  
D
= Date Code  
= Pb−Free Package  
G
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
1
2
3
5
4
V
CC  
OE  
IN A  
GND  
PIN ASSIGNMENT  
1
2
3
4
5
OE  
IN A  
OUT Y  
GND  
OUT Y  
Figure 1. Pinout (Top View)  
V
CC  
FUNCTION TABLE  
A Input  
OE Input  
Y Output  
OE  
IN A  
OUT Y  
H
H
L
L
H
X
L
H
Z
Figure 2. Logic Symbol  
X = Don’t Care  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 − Rev. 5  
NL17SZ126/D  

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