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NL17SZ125P5T5G-L22088 PDF预览

NL17SZ125P5T5G-L22088

更新时间: 2024-11-03 11:01:47
品牌 Logo 应用领域
安森美 - ONSEMI 驱动总线驱动器总线收发器
页数 文件大小 规格书
10页 132K
描述
Single Non-Inverting Buffer, 3-State

NL17SZ125P5T5G-L22088 数据手册

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NL17SZ125  
Non-Inverting 3-State Buffer  
The NL17SZ125 is a high performance noninverting buffer operating  
from a 1.65 V to 5.5 V supply.  
Features  
Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V  
PD  
CC  
http://onsemi.com  
MARKING DIAGRAMS  
Designed for 1.65 V to 5.5 V V Operation  
CC  
Overvoltage Tolerant Inputs and Outputs  
LVTTL Compatible Interface Capability With 5.0 V TTL Logic  
with V = 3.0 V  
CC  
LVCMOS Compatible  
M0 M G  
SC88A (SOT353)  
DF SUFFIX  
G
24 mA Balanced Output Sink and Source Capability  
CASE 419A  
Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
3State OE Input is ActiveLow  
M0 MG  
Replacement for NC7SZ125  
SOT553  
XV5 SUFFIX  
CASE 463B  
G
Chip Complexity = 36 FETs  
These Devices are PbFree and are RoHS Compliant  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
5
1
5
1
M0 MG  
G
TSOP5  
DT SUFFIX  
CASE 483  
1
2
3
5
V
CC  
OE  
IN A  
GND  
M
UDFN6  
1.0 x 1.0  
1
CASE 517BX  
4
OUT Y  
M0  
M
G
= Specific Device Code  
= Date Code  
= PbFree Package  
(*Note: Microdot may be in either location)  
Figure 1. Pinout (Top View)  
*Date Code orientation and/or position may  
vary depending upon manufacturing location.  
OE  
EN  
OUT Y  
IN A  
FUNCTION TABLE  
OE Input  
A Input  
Y Output  
Figure 2. Logic Symbol  
L
L
L
H
X
L
H
Z
H
PIN ASSIGNMENT  
X = Don’t Care  
1
2
3
4
5
OE  
IN A  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
GND  
OUT Y  
V
CC  
©
Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
May, 2012 Rev. 13  
NL17SZ125/D  

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LOGIC GATE|BUFFER|CMOS|TSSOP|6PIN|PLASTIC