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NL17SZ126_12 PDF预览

NL17SZ126_12

更新时间: 2024-11-06 12:22:51
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 114K
描述
Non-Inverting 3-State Buffer

NL17SZ126_12 数据手册

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NL17SZ126  
Non-Inverting 3-State  
Buffer  
The NL17SZ126 is a high performance single noninverting buffer  
operating from a 1.65 V to 5.5 V supply.  
http://onsemi.com  
Features  
Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V  
PD  
CC  
MARKING  
DIAGRAM  
Designed for 1.65 V to 5.5 V V Operation  
CC  
Over Voltage Tolerant Inputs and Outputs  
LVTTL Compatible Interface Capability With 5.0 V TTL Logic  
with V = 3.0 V  
CC  
M2 M G  
SC88A (SOT353)  
G
LVCMOS Compatible  
DF SUFFIX  
CASE 419A  
24 mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
3State OE Input is Active HIGH  
Replacement for NC7SZ126  
M2 MG  
G
SOT553  
XV5 SUFFIX  
CASE 463B  
Chip Complexity = 36 FETs  
These Devices are PbFree and are RoHS Compliant  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
M2 = Specific Device Code  
M
= Date Code  
G
= PbFree Package  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
PIN ASSIGNMENT  
1
2
3
5
4
V
CC  
OE  
IN A  
GND  
1
2
3
4
5
OE  
IN A  
GND  
OUT Y  
V
CC  
OUT Y  
FUNCTION TABLE  
A Input  
OE Input  
Y Output  
Figure 1. Pinout (Top View)  
H
H
L
L
H
X
L
H
Z
X = Don’t Care  
OE  
IN A  
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
Figure 2. Logic Symbol  
©
Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
May, 2012 Rev. 10  
NL17SZ126/D  

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