Datasheet > NL17SZ125_12

NL17SZ125_12

更新时间： 2024-11-02 12:22:51

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
10页	132K
描述
Non-Inverting 3-State Buffer

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中文翻译

获取价格

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NL17SZ125_12 数据手册

NL17SZ125

Non-Inverting 3-State Buffer

The NL17SZ125 is a high performance non−inverting buffer operating

from a 1.65 V to 5.5 V supply.

Features

• Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V

http://onsemi.com

MARKING DIAGRAMS

• Designed for 1.65 V to 5.5 V V Operation

• Overvoltage Tolerant Inputs and Outputs

• LVTTL Compatible − Interface Capability With 5.0 V TTL Logic

with V = 3.0 V

• LVCMOS Compatible

M0 M G

SC−88A (SOT−353)

DF SUFFIX

• 24 mA Balanced Output Sink and Source Capability

CASE 419A

• Near Zero Static Supply Current Substantially Reduces System

Power Requirements

• 3−State OE Input is Active−Low

M0 MG

• Replacement for NC7SZ125

SOT−553

XV5 SUFFIX

CASE 463B

• Chip Complexity = 36 FETs

• These Devices are Pb−Free and are RoHS Compliant

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

M0 MG

TSOP−5

DT SUFFIX

CASE 483

IN A

GND

UDFN6

1.0 x 1.0

CASE 517BX

OUT Y

= Specific Device Code

= Date Code

= Pb−Free Package

(*Note: Microdot may be in either location)

Figure 1. Pinout (Top View)

*Date Code orientation and/or position may

vary depending upon manufacturing location.

OUT Y

IN A

FUNCTION TABLE

OE Input

A Input

Y Output

Figure 2. Logic Symbol

PIN ASSIGNMENT

X = Don’t Care

IN A

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

GND

OUT Y

Semiconductor Components Industries, LLC, 2012

Publication Order Number:

May, 2012 − Rev. 13

NL17SZ125/D

12 3 4 5 6 7...10

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