Datasheet > NL17SZ10MU3TCG

NL17SZ10MU3TCG

更新时间： 2024-11-25 02:51:15

品牌	Logo	应用领域
安森美 - ONSEMI		栅
页数	文件大小	规格书
10页	265K
描述
Single 3-Input NAND Gate

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数据手册

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NL17SZ10MU3TCG 数据手册

Single 3-Input NAND Gate

NL17SZ10

The NL17SZ10 is a single 3−input NAND Gate in three tiny

footprint packages.

Features

• Designed for 1.65 V to 5.5 V V Operation

www.onsemi.com

• 2.4 ns t at V = 5 V (Typ)

• Inputs/Outputs Overvoltage Tolerant up to 5.5 V

MARKING

DIAGRAMS

• I

Supports Partial Power Down Protection

• Source/Sink 24 mA at 3.0 V

OFF

• Chip Complexity < 100 FETs

SC−88

CASE 419B−02

XXXMG

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

IEEC / IEC

SC−74

CASE 318F−05

XXX MG

UDFN6

1.45 x 1.0

CASE 517AQ

Figure 1. Logic Symbol

UDFN6

1.0 x 1.0

CASE 517BX

X M

XX, XXX = Specific Device Code

= Date Code*

= Pb−Free Package

(Note: Microdot may be in either location)

*Date Code orientation and/or position may

vary depending upon manufacturing location.

ORDERING INFORMATION

See detailed ordering, marking and shipping information in the

package dimensions section on page 6 of this data sheet.

Publication Order Number:

October, 2019 − Rev. 0

NL17SZ10/D

12 3 4 5 6 7...10

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与NL17SZ10MU3TCG相关器件

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NL17SZ125/D	ETC	获取价格	Non-Inverting 3-State Buffer
NL17SZ125_05	ONSEMI	获取价格	Non-Inverting 3-State Buffer
NL17SZ125_12	ONSEMI	获取价格	Non-Inverting 3-State Buffer
NL17SZ125_15	ONSEMI	获取价格	Non-Inverting 3-State Buffer