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NDC652 PDF预览

NDC652

更新时间: 2024-11-17 22:29:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管场效应晶体管
页数 文件大小 规格书
10页 248K
描述
P-Channel Logic Level Enhancement Mode Field Effect Transistor

NDC652 数据手册

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March 1996  
NDC652P  
P-Channel Logic Level Enhancement Mode Field Effect Transistor  
General Description  
Features  
-2.4A, -30V. RDS(ON) = 0.18W @ VGS = -4.5V  
RDS(ON) = 0.11W @ VGS = -10V.  
These P-Channel logic level enhancement mode power  
field effect transistors are produced using Fairchild's  
proprietary, high cell density, DMOS technology. This  
very high density process is especially tailored to  
minimize on-state resistance. These devices are  
particularly suited for low voltage applications such as  
notebook computer power management and other  
battery powered circuits where fast high-side switching,  
and low in-line power loss are needed in a very small  
outline surface mount package.  
Proprietary SuperSOTTM-6 package design using copper  
lead frame for superior thermal and electrical capabilities.  
High density cell design for extremely low RDS(ON)  
.
Exceptional on-resistance and maximum DC current  
capability.  
____________________________________________________________________________________________  
4
3
2
1
5
6
Absolute Maximum Ratings  
Symbol Parameter  
TA = 25°C unless otherwise noted  
NDC652P  
-30  
Units  
Drain-Source Voltage  
V
V
A
VDSS  
VGSS  
ID  
Gate-Source Voltage - Continuous  
-20  
Drain Current - Continuous  
- Pulsed  
-2.4  
-10  
PD  
Maximum Power Dissipation  
(Note 1a)  
(Note 1b)  
1.6  
W
1
(Note 1c)  
0.8  
TJ,TSTG Operating and Storage Temperature Range  
-55 to 150  
°C  
THERMAL CHARACTERISTICS  
Thermal Resistance, Junction-to-Ambient (Note 1a)  
R
78  
30  
°C/W  
°C/W  
JA  
q
Thermal Resistance, Junction-to-Case  
(Note 1)  
R
JC  
q
© 1997 Fairchild Semiconductor Corporation  
NDC652P Rev. D1  

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