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NB7L11M PDF预览

NB7L11M

更新时间: 2024-11-14 03:20:55
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
11页 202K
描述
2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination

NB7L11M 数据手册

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NB7L11M  
2.5V/3.3V Differential 1:2  
Clock/Data Fanout Buffer/  
Translator with CML  
Outputs and Internal  
Termination  
http://onsemi.com  
MARKING  
Description  
DIAGRAM*  
The NB7L11M is a differential 1to2 clock/data distribution chip  
with internal source termination and CML output structure, optimized  
for low skew and minimal jitter. The device is functionally equivalent to  
the EP11, LVEP11, or SG11 devices. Device produces two identical  
output copies of clock or data operating up to 8 GHz or 12 Gb/s,  
respectively. As such, NB7L11M is ideal for SONET, GigE, Fiber  
Channel, Backplane and other clock/data distribution applications.  
Inputs incorporate internal 50 W termination resistors and accept  
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).  
Differential 16 mA CML output provides matching internal 50 W  
terminations, and 400 mV output swings when externally terminated,  
16  
1
NB7L  
11M  
QFN16  
MN SUFFIX  
CASE 485G  
ALYWG  
G
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
50 W to V (See Figure 14).  
CC  
The device is offered in a low profile 3x3 mm 16pin QFN package.  
Application notes, models, and support documentation are available at  
www.onsemi.com.  
(Note: Microdot may be in either location)  
Features  
*For additional marking information, refer to  
Application Note AND8002/D.  
Maximum Input Clock Frequency up to 8 GHz Typical  
Maximum Input Data Rate up to 12 Gb/s Typical  
< 0.5 ps of RMS Clock Jitter  
< 10 ps of Data Dependent Jitter  
30 ps Typical Rise and Fall Times  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 10 of this data sheet.  
110 ps Typical Propagation Delay  
3 ps Typical Within Device Skew  
*For additional information on our PbFree strategy and  
soldering details, please download the ON Semicon-  
ductor Soldering and Mounting Techniques Reference  
Manual, SOLDERRM/D.  
Operating Range: V = 2.375 V to 3.465 V with V = 0 V  
CC  
EE  
CML Output Level (400 mV PeaktoPeak Output) Differential  
Output Only  
50 W Internal Input and Output Termination Resistors  
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP  
and SG Devices  
PbFree Packages are Available*  
Q0  
Q0  
V
TCLK  
50 W  
50 W  
CLK  
CLK  
Q1  
Q1  
V
TCLK  
Figure 1. Logic Diagram  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
January, 2006 Rev. 1  
NB7L11M/D  

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