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NB6HQ14MMNTXG

更新时间： 2024-11-30 05:51:55
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
11页 1258K
描述
2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer

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NB6HQ14MMNTXG 数据手册

 浏览型号NB6HQ14MMNTXG的Datasheet PDF文件第2页浏览型号NB6HQ14MMNTXG的Datasheet PDF文件第3页浏览型号NB6HQ14MMNTXG的Datasheet PDF文件第4页浏览型号NB6HQ14MMNTXG的Datasheet PDF文件第5页浏览型号NB6HQ14MMNTXG的Datasheet PDF文件第6页浏览型号NB6HQ14MMNTXG的Datasheet PDF文件第7页 
NB6HQ14M  
2.5V 5GHz / 6.5Gbps  
Differential Input to 1.8V /  
2.5V 1:4 CML Clock / Data  
Fanout Buffer w/ Selectable  
Input Equalizer  
http://onsemi.com  
MARKING  
DIAGRAM*  
Multi−Level Inputs w/ Internal Termination  
16  
Description  
1
The NB6HQ14M is a high performance differential 1:4 CML fanout  
buffer with a selectable Equalizer receiver. When placed in series with  
a Clock /Data path operating up to 5 GHz or 6.5 Gb/s, respectively, the  
NB6HQ14M inputs will compensate the degraded signal transmitted  
across a FR4 PCB backplane or cable interconnect and output four  
identical CML copies of the input signal. Therefore, the serial data rate  
is increased by reducing Inter−Symbol Interference (ISI) caused by  
losses in copper interconnect or long cables. The EQualizer ENable  
pin (EQEN) allows the IN/IN inputs to either flow through or bypass  
the Equalizer section. Control of the Equalizer function is realized by  
setting EQEN; When EQEN is set Low, the IN/IN inputs bypass the  
Equalizer. When EQEN is set High, the IN/IN inputs flow through the  
Equalizer. The default state at start−up is LOW. As such, NB6HQ14M  
is ideal for SONET, GigE, Fiber Channel, Backplane and other  
Clock/Data distribution applications.  
1
NB6H  
Q14M  
ALYWG  
G
QFN−16  
MN SUFFIX  
CASE 485G  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
The differential inputs incorporate internal 50 W termination  
resistors that are accessed through the VT pin. This feature allows the  
NB6HQ14M to accept various logic level standards, such as LVPECL,  
CML or LVDS. The outputs have the flexibility of being powered by  
either a 2.5 V or 1.8 V supply. The 1:4 fanout design was optimized  
for low output skew applications.  
SIMPLIFIED BLOCK DIAGRAM  
The NB6HQ14M is a member of the ECLinPS MAX™ family of  
high performance clock products.  
EQ  
Features  
• Input Data Rate > 6.5 Gb/s  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 10 of this data sheet.  
• Input Clock Frequency > 5 GHz  
• 170 ps Typical Propagation Delay  
• 35 ps Typical Rise and Fall Times  
• < 15 ps Output Skew  
• < 0.8 ps RMS Clock Jitter  
• < 10 ps pp of Data Dependent Jitter  
• Differential CML Outputs, 400 mV Peak−to−Peak, Typical  
• Selectable Input Equalization  
• Operating Range: V = 2.375 V to 2.625 V, V  
= 1.71 V to  
CC  
CCO  
2.625 V  
• Internal Input Termination Resistors, 50 W  
• −40°C to +85°C Ambient Operating Temperature  
• These are Pb−Free Devices  
©
Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
June, 2009 − Rev. 0  
NB6HQ14M/D  
1234567...11

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NB6HQ14MMNTXG 替代型号

型号 品牌 替代类型 描述 数据表
NB6HQ14MMNHTBG ONSEMI

完全替代

 2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer
NB6HQ14MMNG ONSEMI

完全替代

 2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer

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 		2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER
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 		2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer
NB6L11DTR2 ONSEMI

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 		2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER
NB6L11DTR2G ONSEMI

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