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NB3N3010B PDF预览

NB3N3010B

更新时间: 2024-10-02 01:12:59
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
9页 157K
描述
3.3V, 12.288 MHz Audio Oversampling Clock Generator

NB3N3010B 数据手册

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NB3N3010B  
3.3V, 12.288 MHz Audio  
Oversampling Clock  
Generator for USB  
Applications  
http://onsemi.com  
MARKING  
Description  
The NB3N3010B is a precision, low noise clock multiplier that  
generates an output frequency of 12.288 MHz. This is accomplished  
by using FrequencyLockedLoop (FLL) techniques where a 4 kHz  
reference input is multiplied by 3072, or an 8 kHz input by 1536. The  
frequency multiplier is selected by the S0 pin.  
The two LVCMOS output drivers are disabled to a logic Low with  
the ENABLEn pin set HIGH. The NB3N3010B operates from a single  
+3.3 V supply, and is available in the SOIC8 pin package, and  
optionally in a DFN8 package. The operating temperature range is  
from 0°C to +85°C.  
DIAGRAMS*  
8
8
1
3010B  
ALYW  
G
SOIC8  
D SUFFIX  
CASE 751  
1
The NB3N3010B device provides the optimum combination of low  
cost, flexibility, and high performance. This makes it ideal for  
applications such as oversampling AtoD and DtoA converters  
from a low reference frequency, such as a USB startofframe (SOF)  
pulse.  
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
Features  
A
L
Y
= Assembly Location  
= Wafer Lot  
= Year  
Accepts 8 kHz or 4 kHz Reference Input Derived from USB  
StartofFrame  
W = Work Week  
M = Date Code  
Generates 12.288 MHz FrequencyLocked to the Reference  
Fully Integrated FrequencyLockLoop with Internal Loop Filter  
Low Skew Dual LVCMOS Outputs  
Very Low Phase Noise Preserves Codec Noise Floor  
Internal Voltage Regulator  
Supply Voltage Required: +3.3 V $5%  
Temperature Range: 0°C to +85°C  
These are PbFree Devices  
G
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
VDD  
8
CFILT  
5
GND  
4
CLK_A  
6
+1.8 V  
Linear  
Regulator  
REF  
CLK_B  
Output  
Buffers  
Tolerant  
Frequency  
Detector  
3
Frequency  
Generator  
Loop Filter  
7
Divider  
1
2
ENABLEn  
S0  
Figure 1. NB3N3010B Simplified Diagram  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 Rev. 0  
NB3N3010B/D  
 

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