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NB3N3020 PDF预览

NB3N3020

更新时间: 2024-11-23 05:51:55
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
8页 131K
描述
3.3 V, LV-PECL/LV-CMOS Clock Multiplier

NB3N3020 数据手册

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NB3N3020  
3.3 V, LV-PECL/LV-CMOS  
Clock Multiplier  
Description  
The NB3N3020 is a high precision, low phase noise selectable clock  
multiplier. The device takes a 5 – 27 MHz fundamental mode parallel  
resonant crystal or a 2 210 MHz LVCMOS single ended clock source  
and generates a differential LVPECL output and a single ended  
LVCMOS/LVTTL output at a selectable clock output frequency which  
is a multiple of the input clock frequency. Three trilevel (Low, Mid,  
High) LVCMOS/LVTTL single ended select pins set one of 26  
possible clock multipliers. An LVCMOS/LVTTL output enable (OE)  
tristates clock outputs when low.  
http://onsemi.com  
MARKING  
DIAGRAM  
16  
16  
NB3N  
3020  
ALYWG  
G
1
TSSOP16  
DT SUFFIX  
CASE 948F  
1
This device is housed in 5 mm x 4.4 mm narrow body TSSOP 16 pin  
package.  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
Features  
Selectable Clock Multiplier  
External Loop Filter is Not Required  
LVPECL Differential Output  
(Note: Microdot may be in either location)  
LVCMOS/ LVTTL Outputs  
RMS Period Jitter of 5 ps  
Jitter or Low Phase Noise at 125 MHz [25 MHz Input]:  
PIN CONFIGURATION  
Offset  
100 Hz  
Noise Power  
-95 dBc/Hz  
-107 dBc/Hz  
-112 dBc/Hz  
-117 dBc/Hz  
-117 dBc/Hz  
-134 dBc/Hz  
1
16  
VDD  
X1/CLK  
X2  
OE2  
VDD  
CLK2  
CLK2  
GND  
VDD  
CLK1  
GND  
1 kHz  
10 kHz  
100 kHz  
1 MHz  
10 MHz  
Sel2  
Sel1  
Sel0  
OE1  
Operating Range 3.3 V 10%  
Industrial Temperature Range 40°C to +85°C  
GND  
(Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2008  
1
Publication Order Number:  
September, 2008 Rev. 0  
NB3N3020/D  

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