NB3N51032
3.3 V, Crystal to 25 MHz,
100 MHz, 125 MHz and
200 MHz Dual HCSL/LVDS
Clock Generator
The NB3N51032 is a precision, low phase noise clock generator that
supports PCI Express and Ethernet requirements. The device accepts a
25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 10). The NB3N51032 provides selectable
spread options of −0.5% and −0.75% for applications demanding low
Electromagnetic Interference (EMI) as well as optimum performance
with no spread option.
www.onsemi.com
MARKING
DIAGRAM
16
16
NB3N
1032
ALYWG
G
1
TSSOP−16
DT SUFFIX
CASE 948F
1
Features
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
• External Loop Filter is Not Required
• HCSL Differential Output or LVDS with Proper Termination
• Four Selectable Multipliers of the Input Frequency
• Output Enable with Tri−State Outputs
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
• PCIe Gen 1, Gen 2, Gen 3, Gen 4 Compliant
• Spread of −0.5%, −0.75% and No Spread
Applications
• Phase Noise: @ 100 MHz
Offset Noise Power
100 Hz −88 dBc/Hz
1 kHz −118 dBc/Hz
10 kHz −131 dBc/Hz
100 kHz −132 dBc/Hz
1 MHz −144 dBc/Hz
10 MHz −155 dBc/Hz
• Networking
• Consumer
• Computing and Peripherals
• Industrial Equipment
• PCIe Clock Generation Gen 1, Gen 2, Gen 3 and Gen 4
• Gigabit Ethernet
• FB DIMM
• Typical Period Jitter RMS of 1.5 ps
• Operating Supply Voltage Range 3.3 V 5%
• Industrial Temperature Range −40°C to +85°C
• Functionally Compatible with IDT557−03,
IDT5V41065, IDT5V41235 with enhanced performance
• These are Pb−Free Devices
End Products
• Switch and Router
• Set Top Box, LCD TV
• Servers, Desktop Computers
• Automated Test Equipment
V
DD
SS0 SS1
Spread Spectrum
Circuit
X1/CLK
Clock Buffer
Crystal Oscillator
Phase
Detector
Charge
Pump
CLK0
CLK0
HCSL
Output
VCO
25 MHz Clock or
Crystal
X2
CLK1
CLK1
HCSL
Output
BN
V
= VDDODA = VDDXD
DD
GND
S0
S1
OE IREF
GND = GNDODA = GNDXD
Figure 1. NB3N51032 Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
September, 2017 − Rev. 3
NB3N51032/D