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NB3N551DG PDF预览

NB3N551DG

更新时间: 2024-01-14 09:29:48
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 117K
描述
3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer

NB3N551DG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.08
系列:3N输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.025 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:6 ns传播延迟(tpd):3 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.16 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mm最小 fmax:180 MHz
Base Number Matches:1

NB3N551DG 数据手册

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NB3N551  
3.3 V / 5.0 V  
Ultra−Low Skew  
1:4 Clock Fanout Buffer  
Description  
http://onsemi.com  
MARKING  
The NB3N551 is a low skew 1to 4 clock fanout buffer, designed  
for clock distribution in mind. The NB3N551 specifically guarantees  
low outputtooutput skew. Optimal design, layout and processing  
minimize skew within a device and from device to device.  
DIAGRAMS*  
8
The output enable (OE) pin threestates the outputs when low.  
SOIC8  
D SUFFIX  
CASE 751  
3N551  
ALYW  
G
8
Features  
1
1
Input/Output Clock Frequency up to 180 MHz  
Low Skew Outputs (50 ps typical)  
3N551 = Specific Device Code  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
Output goes to ThreeState Mode via OE  
Operating Range: V = 3.0 V to 5.5 V  
DD  
Ideal for Networking Clocks  
Packaged in 8pin SOIC  
Industrial Temperature Range  
These are PbFree Devices  
DFN8  
MN SUFFIX  
CASE 506AA  
1
4
1
6K = Specific Device Code  
Q1  
M
= Date Code  
G
= PbFree Package  
Q2  
(Note: Microdot may be in either location)  
CLK  
*For additional marking information, refer to  
Application Note AND8002/D.  
Q3  
Q4  
PIN CONNECTIONS  
1
2
3
4
8
7
6
5
OE  
V
I
CLK  
OE  
Q1  
DD  
Figure 1. Block Diagram  
GND  
Q4  
Q2  
Q3  
ORDERING INFORMATION  
Device  
Package  
Shipping  
NB3N551DG  
SOIC8  
98 Units/Rail  
(PbFree)  
NB3N551DR2G  
SOIC8  
(PbFree)  
2500/Tape & Reel  
1000/Tape & Reel  
NB3N551MNR4G  
DFN8  
(PbFree)  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
October, 2006 Rev. 2  
NB3N551/D  

NB3N551DG 替代型号

型号 品牌 替代类型 描述 数据表
NB3N551MNR4G ONSEMI

完全替代

3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer
NB3N551DR2G ONSEMI

完全替代

3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer
CY2304SXC-1 CYPRESS

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