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NB3RL02FCT2G PDF预览

NB3RL02FCT2G

更新时间: 2024-02-06 12:23:57
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 99K
描述
Low Phase-Noise Two-Channel Clock Fanout Buffer

NB3RL02FCT2G 数据手册

 浏览型号NB3RL02FCT2G的Datasheet PDF文件第2页浏览型号NB3RL02FCT2G的Datasheet PDF文件第3页浏览型号NB3RL02FCT2G的Datasheet PDF文件第4页浏览型号NB3RL02FCT2G的Datasheet PDF文件第5页浏览型号NB3RL02FCT2G的Datasheet PDF文件第6页浏览型号NB3RL02FCT2G的Datasheet PDF文件第7页 
NB3RL02  
Low Phase-Noise  
Two-Channel Clock Fanout  
Buffer  
The NB3RL02 is a low−skew, low jitter 1:2 clock fan−out buffer,  
ideal for use in portable end−equipment, such as mobile phones. With  
integrated LDO and output control circuitry.  
www.onsemi.com  
The MCLK_IN pin has an AC coupling capacitor and will directly  
accept a square or sine wave clock input, such as a temperature  
compensated crystal oscillator (TCXO). The minimum acceptable  
input amplitude of the sine wave is 300 mV peak−to−peak.  
The two clock outputs are enabled by control inputs CLK_REQ1  
and CLK_REQ2.  
MARKING  
DIAGRAMS  
WLCSP8  
CASE 499BQ  
RLYYWW  
G
The NB3RL02 has an integrated Low−Drop−Out (LDO) voltage  
regulator which accepts input voltages from 2.3 V to 5.5 V and outputs  
1.8 V at I = 50 mA. This 1.8 V supply is externally available to  
out  
RL  
YY  
WW  
G
= Specific Device Code  
= Year  
= Work Week  
provide regulated power to peripheral devices, such as a TCXO.  
The adaptive clock output buffers offer controlled slew−rate over a  
wide capacitive loading range which minimizes EMI emissions,  
maintains signal integrity, and minimizes ringing caused by signal  
reflections on the clock distribution lines.  
= Pb−Free Package  
The NB3RL02 is offered in a 0.4 mm pitch wafer−level−chip−scale  
(WLCS) package and is optimized for very low standby current  
consumption.  
LOGIC DIAGRAM  
Features  
Low Additive Noise:  
−149 dBc/Hz at 10 kHz Offset Phase Noise  
0.37 ps (rms) Output Jitter  
Limited Output Slew Rate for EMI Reduction  
(1 ns to 5 ns/Rise/Fall Time for 10−50 pF Loads)  
Regulated 1.8 V Output Supply Available for External Clock Source,  
ie. TCX0  
Ultra−Small Package:  
8−ball: 0.4 mm Pitch WLCS  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
ESD Performance Exceeds JESD 22  
2000 V Human−Body Model (A114−A)  
200 V Machine Model (A115−A)  
1000 V Charged−Device Model (JESD22−C101−A Level III)  
These are Pb−Free Devices  
Applications  
Cellular Phones  
Global Positioning Systems (GPS)  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
September, 2015 − Rev. 3  
NB3RL02/D  

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