Datasheet > NB3N51034

NB3N51034

更新时间： 2024-01-27 17:26:44

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
9页	397K
描述
Quad HCSL/LVDS Clock Generator

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中文翻译

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数据手册

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NB3N51034 数据手册

NB3N51034

3.3V, Crystal to 100MHz/

200MHz Quad HCSL/LVDS

Clock Generator

The NB3N51034 is a high precision, low phase noise clock generator

that supports spread spectrum designed for PCI Express applications.

This device takes a 25 MHz fundamental mode parallel resonant crystal

and generates 4 differential HCSL/LVDS outputs at 100 MHz or

200 MHz (See Figure 6 for LVDS interface). The NB3N51034 provides

selectable spread options of −0.5%, −1.0%, −1.5%, for applications

demanding low Electromagnetic Interference (EMI). No spread setting

is also available.

http://onsemi.com

MARKING

DIAGRAM

NB3N

1034

ALYWG

Features

• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal

• Power Down Mode

• 4 Low Skew HCSL or LVDS Outputs

• OE Tri−States Outputs

TSSOP−20

DT SUFFIX

CASE 948E

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• Spread of −0.5%, −1.0%, −1.5% and No Spread

• PCIe Gen 1, 2, 3 Jitter Compliant

• Phase Noise (SS OFF) @ 100 MHz:

(Note: Microdot may be in either location)

Offset

100 Hz

1 kHz

Noise Power

−110 dBc/Hz

−123 dBc/Hz

−134 dBc/Hz

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

10 kHz

100 kHz −137 dBc/Hz

1 MHz −138 dBc/Hz

10 MHz −154 dBc/Hz

• Operating Range 3.3 V 5%

• Industrial Temperature Range −40°C to +85°C

• Functionally Compatible with IDT557−05,

IDT5V41066, IDT5V41236

• Computing and Peripherals

• Industrial Equipment

• PCIe Clock Generation Gen I, Gen II and Gen III

End Products

• These are Pb−Free Devices

• Switch and Router

Applications

• Networking

• Consumer

• Set Top Box, LCD TV

• Servers, Desktop Computers

• Automated Test Equipment

VDD

S0 S1 S2

CLK0

HCSL

Output

Spread Spectrum

Circuit

CLK1

HCSL

Output

X1/CLK

Clock Buffer

Crystal Oscillator

CLK2

Phase

Detector

Charge

Pump

HCSL

Output

VCO

25 MHz Clock

or Crystal

CLK3

HCSL

Output

GND

IREF

Figure 1. NB3N51034 Simplified Logic Diagram

Publication Order Number:

October, 2013 − Rev. 1

NB3N51034/D

12 3 4 5 6 7...9

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