NB3N551

更新时间： 2024-11-26 03:47:03

品牌	Logo	应用领域
安森美 - ONSEMI		时钟
页数	文件大小	规格书
5页	117K
描述
3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer

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NB3N551 数据手册

NB3N551

3.3 V / 5.0 V

Ultra−Low Skew

1:4 Clock Fanout Buffer

Description

http://onsemi.com

MARKING

The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed

for clock distribution in mind. The NB3N551 specifically guarantees

low output−to−output skew. Optimal design, layout and processing

minimize skew within a device and from device to device.

DIAGRAMS*

The output enable (OE) pin three−states the outputs when low.

SOIC−8

D SUFFIX

CASE 751

3N551

ALYW

Features

• Input/Output Clock Frequency up to 180 MHz

• Low Skew Outputs (50 ps typical)

3N551 = Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• Output goes to Three−State Mode via OE

• Operating Range: V = 3.0 V to 5.5 V

• Ideal for Networking Clocks

• Packaged in 8−pin SOIC

• Industrial Temperature Range

• These are Pb−Free Devices

DFN8

MN SUFFIX

CASE 506AA

6K = Specific Device Code

= Date Code

= Pb−Free Package

(Note: Microdot may be in either location)

CLK

*For additional marking information, refer to

Application Note AND8002/D.

PIN CONNECTIONS

CLK

Figure 1. Block Diagram

GND

ORDERING INFORMATION

†

Device

Package

Shipping

NB3N551DG

SOIC−8

98 Units/Rail

(Pb−Free)

NB3N551DR2G

SOIC−8

(Pb−Free)

2500/Tape & Reel

1000/Tape & Reel

NB3N551MNR4G

DFN−8

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Publication Order Number:

October, 2006 − Rev. 2

NB3N551/D

12 3 4 5

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