NB3N502DEVB

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NB3N502DEVB 数据手册

NB3N502DEVB

NB3N502 Evaluation Board

User’s Manual

http://onsemi.com

Description

The NB3N502 Evaluation Board was designed to provide

a flexible and convenient platform to quickly evaluate,

characterize and verify the performance and operation of the

NB3N502 PLL Clock Multiplier. This user’s manual

provides detailed information on the board’s contents,

layout and use, and it should be used in conjunction with the

NB3N502 data sheet which contains full technical details on

device specifications and operation (www.onsemi.com).

• Supports the Use of a 5 MHz to 27 MHz Through−hole

or Surface Mount Crystal

• SMA Connectors are Provided for Auxiliary Input and

Output Interfaces

• Incorporates Onboard Slide Switch Controlled

Multiplier Select Pins, Minimizing Excess Cabling

This Evaluation Board Manual Contains

• Information on the NB3N502 Evaluation Board

• Appropriate Lab Setup

• Evaluation Board Layout

• Bill of Materials

Board Features

• Fully Assembled Evaluation Board

• Accommodates the Electrical Characterization of the

NB3N502 in the SOIC−8 Package

Figure 1. NB3N502 Evaluation Board

Publication Order Number:

October, 2006 − Rev. 0

NB3N502DEVB/D

12 3 4 5 6 7

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