Datasheet > NB3N3020DTGEVB

NB3N3020DTGEVB

更新时间： 2024-10-02 01:23:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
9页	136K
描述
3.3 V, LVPECL/LVCMOS Clock Multiplier

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NB3N3020DTGEVB 数据手册

NB3N3020

3.3 V, LVPECL/LVCMOS

Clock Multiplier

Description

The NB3N3020 is a high precision, low phase noise selectable clock

multiplier. The device takes a 5 – 27 MHz fundamental mode parallel

resonant crystal or a 2 − 210 MHz LVCMOS single ended clock source

and generates a differential LVPECL output and a single ended

LVCMOS/LVTTL output at a selectable clock output frequency which

is a multiple of the input clock frequency. Three tri−level (Low, Mid,

High) LVCMOS/LVTTL single ended select pins set one of 26

possible clock multipliers. The LVCMOS/LVTTL output enable

(OE1) tri−states the LVCMOS/LVTTL clock output (CLK1) when

low. When the LVTTL/LVCMOS output enable (OE2) is LOW,

LVPECL CLK2 is forced LOW and LVPECL CLK2 is forced HIGH.

This device is housed in 5 mm x 4.4 mm narrow body TSSOP 16 pin

package.

http://onsemi.com

MARKING

DIAGRAM

NB3N

3020

ALYWG

TSSOP−16

DT SUFFIX

CASE 948F

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Features

• Selectable Clock Multiplier

• External Loop Filter is Not Required

• LVPECL Differential Output

• LVCMOS/ LVTTL Outputs

• RMS Period Jitter of 5 ps

(*Note: Microdot may be in either location)

PIN CONFIGURATION

VDD

X1/CLK

OE2

• Jitter or Low Phase Noise at 125 MHz [25 MHz Input]:

VDD

CLK2

GND

VDD

CLK1

GND

Offset

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

10 MHz

Noise Power

−95 dBc/Hz

−107 dBc/Hz

−112 dBc/Hz

−117 dBc/Hz

−134 dBc/Hz

Sel2

Sel1

Sel0

OE1

GND

(Top View)

• Operating Range 3.3 V 10%

• Industrial Temperature Range −40°C to +85°C

• These are Pb−Free Devices

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

Publication Order Number:

January, 2014 − Rev. 4

NB3N3020/D

12 3 4 5 6 7...9

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