Datasheet > NB3N501

NB3N501

更新时间： 2024-11-23 12:22:47

品牌	Logo	应用领域
安森美 - ONSEMI		时钟
页数	文件大小	规格书
6页	139K
描述
3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier

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NB3N501 数据手册

NB3N501

3.3V / 5.0V 13 MHz to

160 MHz PLL Clock

Multiplier

Description

http://onsemi.com

MARKING DIAGRAM

The NB3N501 is a clock multiplier that will generate one of nine

selectable output multiples of an input frequency via two 3−level

select inputs (S0, S1). It accepts a standard fundamental mode crystal

or an external reference clock signal. Phase−Locked−Loop (PLL)

design techniques are used to produce a low jitter, TTL level clock

output up to 160 MHz with a 50% duty cycle. An Output Enable (OE)

pin is provided, and when asserted low, the clock output goes into

tri−state (high impedance). The NB3N501 is commonly used in

electronic systems as a cost efficient replacement for crystal

oscillators

3N501

ALYWG

SOIC−8

D SUFFIX

CASE 751

3N501 = Specific Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Features

• Clock Output Frequencies up to 160 MHz

• Nine Selectable Multipliers of the Input Frequency

• Operating Range: V = 3.3 V ± 10% or 5.0 V ± 5%

• Low Jitter Output of 25 ps One Sigma (rms)

• Zero ppm Clock Multiplication Error

• 45% − 55% Output Duty Cycle

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

• TTL/CMOS Output with 25 mA TTL Level Drive

• Crystal Reference Input Range of 5 − 27 MHz

• Input Clock Frequency Range of 2 − 50 MHz

• OE, Output Enable with Tri−State Output

• 8−Pin SOIC

• Industrial Temperature Range −40°C to +85°C

• These are Pb−Free Devices

X1/ICLK

Crystal

crystal or

clock

TTL/

CMOS

Output

÷ P

Phase

Detector

Charge

Pump

Oscillator

VCO

CLKOUT

LX1

LX2

Multiplier

Select

Feedback

÷ M

S1 S0

GND

Figure 1. NB3N501 Logic Diagram

Publication Order Number:

May, 2012 − Rev. 1

NB3N501/D

12 3 4 5 6

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