Datasheet > NB3N4666C

NB3N4666C

更新时间： 2024-11-24 01:12:19

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
10页	121K
描述
3.3 V Quad LVCMOS Differential Line Receiver Translator

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中文翻译

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NB3N4666C 数据手册

NB3N4666C

3.3 V Quad LVCMOS

Differential Line Receiver

Translator

Description

www.onsemi.com

The NB3N4666C is a quad−channel LVDS line receiver/translator

offering data rates up to 400 Mbps (200 MHz) and low power

consumption. The NB3N4666C receiver incorporates input fail−safe

protection circuit that provides a known output voltage under input

open−circuit and terminated (100 W) conditions. The four independent

inputs accept differential signals such as: M−LVDS, LVDS, LVPECL

and HCSL and translates them to a single−ended, 3.3 V LVCMOS.

The NB3N4666C also offers active high and active low

enable/disable inputs (EN and EN) that allow users to control outputs

of all four receivers. These inputs enable or disable the receivers and

switch the outputs to an active or high impedance state respectively

(see Table 2). The high impedance mode feature helps to reduce the

quiescent power consumption to less than 10 mW typical, when the

outputs of one or more NB3N4666C devices are multiplexed together.

MARKING

DIAGRAMS

NB3N

4666

ALYWG

TSSOP−16

DT SUFFIX

CASE 948F

= Assembly Location

= Wafer Lot

= Year

W = Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

Features

• Accepts M−LVDS, LVDS, LVPECL and HCSL Differential Input

Signal Levels

NB3N4666C

VCC

IN4

• Maximum Data Rate of 400 Mbps

• Maximum Clock Frequency of 200 MHz

IN1

IN4

• 25 ps Typical Channel−to−Channel Skew

• 3.3 ns Maximum Propagation Delay

• 3.3 V 10% Power Supply

OUT4

OUT1

• High Impedance Outputs When Disabled

♦ Low Quiescent Power < 10 mW Typical

• Supports Open and Terminated Input Fail−safe

• −40°C to +85°C Ambient Operating Temperature

OUT2

OUT3

• 16−Pin TSSOP, 5.0 mm x 4.4 mm x 1.2 mm

• These are Pb−Free Devices

IN3

IN2

Applications

• Point−to−point Data Transmission

• Backplane Receivers

• Clock Distribution Networks

• Multidrop Buses

GND

Figure 1. Functional Block Diagram

ORDERING INFORMATION

See detailed ordering and shipping information on page 8 of

this data sheet.

Publication Order Number:

July, 2017 − Rev. 1

NB3N4666C/D

12 3 4 5 6 7...10

中文翻译

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与NB3N4666C相关器件

型号	品牌	获取价格	描述	数据表
NB3N4666C_17	ONSEMI	获取价格	3.3 V Quad LVCMOS Differential Line Receiver Translator
NB3N4666CDTR2G	ONSEMI	获取价格	3.3 V Quad LVCMOS Differential Line Receiver Translator
NB3N501	ONSEMI	获取价格	3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier
NB3N501DG	ONSEMI	获取价格	3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier
NB3N501DR2G	ONSEMI	获取价格	3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier
NB3N502	ONSEMI	获取价格	14 MHz to 190 MHz PLL Clock Multiplier
NB3N502DEVB	ONSEMI	获取价格	NB3N502 Evaluation Board
NB3N502DG	ONSEMI	获取价格	14 MHz to 190 MHz PLL Clock Multiplier
NB3N502DR2G	ONSEMI	获取价格	14 MHz to 190 MHz PLL Clock Multiplier
NB3N508S	ONSEMI	获取价格	3.3V, 216 MHz PureEdge VCXO Clock Generator with M−LVDS Output

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