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MTP50N06EN PDF预览

MTP50N06EN

更新时间: 2024-11-05 13:11:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
8页 182K
描述
50 A, 60 V, 0.025 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB

MTP50N06EN 技术参数

生命周期:Obsolete包装说明:FLANGE MOUNT, R-PSFM-T3
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.69外壳连接:DRAIN
配置:SINGLE最小漏源击穿电压:60 V
最大漏极电流 (ID):50 A最大漏源导通电阻:0.025 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJEDEC-95代码:TO-220AB
JESD-30 代码:R-PSFM-T3元件数量:1
端子数量:3工作模式:ENHANCEMENT MODE
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FLANGE MOUNT极性/信道类型:N-CHANNEL
功耗环境最大值:150 W认证状态:Not Qualified
表面贴装:NO端子形式:THROUGH-HOLE
端子位置:SINGLE晶体管元件材料:SILICON
Base Number Matches:1

MTP50N06EN 数据手册

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Order this document  
by MTP50N06V/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
N–Channel Enhancement–Mode Silicon Gate  
TMOS POWER FET  
42 AMPERES  
60 VOLTS  
TMOS V is a new technology designed to achieve an on–resis-  
tance area product about one–half that of standard MOSFETs. This  
new technology more than doubles the present cell density of our  
50 and 60 volt TMOS devices. Just as with our TMOS E–FET  
designs, TMOS V is designed to withstand high energy in the  
avalanche and commutation modes. Designed for low voltage, high  
speed switching applications in power supplies, converters and  
power motor controls, these devices are particularly well suited for  
bridge circuits where diode speed and commutating safe operating  
areas are critical and offer additional safety margin against  
unexpected voltage transients.  
R
= 0.028 OHM  
DS(on)  
TM  
D
New Features of TMOS V  
On–resistance Area Product about One–half that of Standard  
MOSFETs with New Low Voltage, Low R Technology  
DS(on)  
Faster Switching than E–FET Predecessors  
G
Features Common to TMOS V and TMOS E–FETS  
S
Avalanche Energy Specified  
and V Specified at Elevated Temperature  
Static Parameters are the Same for both TMOS V and  
TMOS E–FET  
CASE 221A–06, Style 5  
TO–220AB  
I
DSS  
DS(on)  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
60  
Unit  
Vdc  
Vdc  
Drain–Source Voltage  
V
DSS  
Drain–Gate Voltage (R  
= 1.0 M)  
Gate–Source Voltage — Continuous  
V
DGR  
60  
GS  
V
± 20  
± 25  
Vdc  
Vpk  
GS  
Gate–Source Voltage — Non–Repetitive (t 10 ms)  
V
GSM  
p
Drain Current — Continuous @ 25°C  
Drain Current — Continuous @ 100°C  
I
I
42  
30  
147  
Adc  
Apk  
D
D
Drain Current — Single Pulse (t 10 µs)  
I
p
DM  
Total Power Dissipation @ 25°C  
Derate above 25°C  
P
D
125  
0.83  
Watts  
W/°C  
Operating and Storage Temperature Range  
T , T  
stg  
55 to 175  
400  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V = 10 Vdc, I = 42 Apk, L = 0.454 µH, R = 25 )  
GS L G  
Thermal Resistance — Junction to Case  
Thermal Resistance — Junction to Ambient  
R
θJC  
R
θJA  
1.2  
62.5  
°C/W  
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds  
T
L
260  
°C  
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 3  
Motorola, Inc. 1996  

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