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MTP52N06V PDF预览

MTP52N06V

更新时间： 2024-01-27 01:57:32
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 晶体晶体管功率场效应晶体管开关脉冲局域网
页数 文件大小 规格书
8页 166K
描述
TMOS POWER FET 52 AMPERES 60 VOLTS RDS(on) = 0.022 OHM

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MTP52N06V 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TO-220AB包装说明：LEAD FREE, CASE 221A-09, 3 PIN
针数：3Reach Compliance Code：not_compliant
ECCN代码：EAR99风险等级：5.32
其他特性：AVALANCHE RATED, LOGIC LEVEL COMPATIBLE雪崩能效等级（Eas）：406 mJ
外壳连接：DRAIN配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：60 V最大漏极电流 (Abs) (ID)：52 A
最大漏极电流 (ID)：52 A最大漏源导通电阻：0.025 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJEDEC-95代码：TO-220AB
JESD-30 代码：R-PSFM-T3JESD-609代码：e3
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：175 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：FLANGE MOUNT峰值回流温度（摄氏度）：260
极性/信道类型：N-CHANNEL最大功率耗散 (Abs)：165 W
最大脉冲漏极电流 (IDM)：182 A认证状态：Not Qualified
子类别：FET General Purpose Powers表面贴装：NO
端子面层：Tin (Sn)端子形式：THROUGH-HOLE
端子位置：SINGLE处于峰值回流温度下的最长时间：40
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

MTP52N06V 数据手册

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Order this document  
by MTP52N06V/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
N–Channel Enhancement–Mode Silicon Gate  
TMOS POWER FET  
52 AMPERES  
60 VOLTS  
TMOS V is a new technology designed to achieve an on–resis-  
tance area product about one–half that of standard MOSFETs. This  
new technology more than doubles the present cell density of our  
50 and 60 volt TMOS devices. Just as with our TMOS E–FET  
designs, TMOS V is designed to withstand high energy in the  
avalanche and commutation modes. Designed for low voltage, high  
speed switching applications in power supplies, converters and  
power motor controls, these devices are particularly well suited for  
bridge circuits where diode speed and commutating safe operating  
areas are critical and offer additional safety margin against  
unexpected voltage transients.  
R
= 0.022 OHM  
DS(on)  
TM  
D
New Features of TMOS V  
•
On–resistance Area Product about One–half that of Standard  
MOSFETs with New Low Voltage, Low R Technology  
DS(on)  
Faster Switching than E–FET Predecessors  
•
G
Features Common to TMOS V and TMOS E–FETS  
S
•
•
•
Avalanche Energy Specified  
and V Specified at Elevated Temperature  
Static Parameters are the Same for both TMOS V and TMOS E–FET  
CASE 221A–06, Style 5  
TO–220AB  
I
DSS  
DS(on)  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
60  
Unit  
Vdc  
Vdc  
Drain–Source Voltage  
V
DSS  
Drain–Gate Voltage (R  
= 1.0 MΩ)  
V
DGR  
60  
GS  
Gate–Source Voltage — Continuous  
Gate–Source Voltage — Non–Repetitive (t ≤ 10 ms)  
V
± 20  
± 25  
Vdc  
Vpk  
GS  
V
GSM  
p
Drain Current — Continuous  
Drain Current — Continuous @ 100°C  
Drain Current — Single Pulse (t ≤ 10 µs)  
I
I
52  
41  
182  
Adc  
Apk  
D
D
I
p
DM  
Total Power Dissipation  
Derate above 25°C  
P
D
188  
1.25  
Watts  
W/°C  
Operating and Storage Temperature Range  
T , T  
stg  
–55 to 175  
406  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V  
= 10 Vdc, I = 52 Apk, L = 0.3 mH, R = 25 Ω)  
GS L G  
Thermal Resistance — Junction to Case  
Thermal Resistance — Junction to Ambient  
R
R
0.8  
62.5  
°C/W  
°C  
θJC  
θJA  
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds  
T
260  
L
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 3  
Motorola, Inc. 1996  
12345678

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