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MT90840AK PDF预览

MT90840AK

更新时间: 2024-11-22 22:38:35
品牌 Logo 应用领域
MITEL 开关
页数 文件大小 规格书
4页 102K
描述
Distributed Hyperchannel Switch

MT90840AK 数据手册

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MT90840  
Distributed Hyperchannel Switch  
Advance Information  
ISSUE 1  
June 1995  
Features  
Time-slot interchange function between 8 pairs  
of ST-BUS/GCI/MVIP streams (512 channels)  
and a Parallel Data Port (PDP)  
Ordering Information  
MT90840AK  
MT90840AP  
100 Pin PQFP  
84 Pin PLCC  
Supports star, point to point connections and  
unidirectional or bidirectional ring topologies for  
distributed systems  
-40°C to 85°C  
Input to Output Bypass function with minimum  
delay for shared ring applications  
Special diagnostic alarm functions for statistical  
analysis  
Provides an internal latency adjustment buffer  
for ring applications  
JTAG boundary scan  
Applications  
Parallel port data rates up to 19.44Mbyte/s  
Bridging ST-BUS/MVIP buses to high speed  
Time Division Multiplex backplanes at SONET  
rates (STS-1/3)  
Programmable data rates on the serial port side  
(2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s)  
Unidirectional Parallel switching mode for up to  
2430 channels non-blocking  
High speed isochronous backbones for  
distributed PBX and Local Area Network  
systems  
Per-channel direction control on the serial port  
side  
Switch platforms of up to 2430 channels with  
guaranteed frame integrity for wideband  
channels  
Per-channel message mode and high-  
impedance control on both parallel and serial  
port sides  
Serial bus control and monitoring  
Data multiplexer  
8-bit multiplexed port compatible with Intel and  
Motorola microcontrollers  
Guarantees frame integrity when switching  
wideband channels such as ISDN H0 channel  
High speed communications interface  
Isochronous switching/multiplexing to support  
IEEE 802.9 standards  
Provides external control lines allowing the fast  
parallel interface to be shared with other  
devices  
C4OUT  
C4REF1  
PPFRo  
SERIAL PORT TIMING  
PARALLEL PORT TIMING  
CONTROL  
PCKT  
PPFRi  
PCKR  
CONTROL  
C4REF2  
FO  
RECEIVE PATH  
DATA & CONN  
MEMORIES  
RECEIVE  
LATENCY  
BUFFER  
PDi0-7  
DSo[0:7]  
S-P  
PARALLEL  
PORT  
INTERFACE  
Serial  
Data  
Parallel  
Data  
&
DSi[0:7]  
P-S  
PDo0-7  
Port  
Port  
TRANSMIT PATH  
DATA & CONN  
MEMORIES  
TCK  
TMS  
TDI  
EXTERNAL  
CONTROL  
CT0  
CT1  
CT2  
JTAG  
TDO  
Microprocessor Interface  
CT3  
WR/ RD/  
R/W DS  
INT  
CS DTACK  
RESET  
ALE  
AD[0:7]  
Figure 1 - Functional Block Diagram  
2-189  

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