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MT9085

更新时间: 2024-11-23 04:14:11
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
20页 288K
描述
CMOS PAC - Parallel Access Circuit

MT9085 数据手册

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CMOS MT9085  
PAC - Parallel Access Circuit  
ISSUE 3  
January 1993  
Features  
Configurable for parallel-to-serial or  
serial-to-parallel conversion of 1024 channels  
Ordering Information  
MT9085AP  
68 Pin PLCC  
Interfaces to Mitel’s MT9080 Switch Matrix  
Module (SMX). Generates all framing signals  
required in 1K or 2K switching applications  
-40°C to 70°C  
Serial data rates of 2.048 Mbit/s or 4.096 Mbit/s  
Mitel ST-BUS compatible serial inputs/outputs  
Description  
The MT9085 Parallel Access Circuit (PAC) provides  
an interface between an 8 bit, parallel time division  
multiplexed bus and  
a
serial time division  
Applications  
multiplexed bus. A single PAC device will accept  
data clocked out on the parallel bus of the Mitel  
MT9080 (SMX) and output it on 32/16 time division  
multiplexed serial bus streams. A second device can  
be configured to perform the conversion from the  
serial format into an SMX compatible parallel format.  
The time division, serial multiplexed streams may  
operate at 2.048 Mbit/s or at 4.096 Mbit/s. The PAC  
generates all framing signals required by the SMX  
for 1024 and 2048 channel configurations.  
Interfacing the MT9080 Switch Matrix Module to  
an ST-BUS system  
Rate conversion between 4 Mbit/s and 2 Mbit/s  
serial streams  
Interfacing a parallel system bus to devices  
utilizing serial I/O  
S0  
S1  
P0  
P7  
C4i  
F0i  
C16i  
Shift  
Registers  
Timing  
Generation  
C2o  
C4o  
F0o  
DFPo  
DFPo  
CFPo  
Address  
Decoder  
C16  
C4  
LOAD  
C16  
OE  
MCA  
MCB  
CKD  
C4  
Mode  
Control  
Parallel/Serial  
S30  
S31  
2/4S  
VSS  
VDD  
Figure 1 - Functional Block Diagram  
2-125  

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