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MT90863AL1 PDF预览

MT90863AL1

更新时间: 2024-11-23 20:01:15
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信电信集成电路
页数 文件大小 规格书
46页 376K
描述
Digital Time Switch, CMOS, PQFP128, 28 X 28 MM, 3.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-022DB, MQFP-128

MT90863AL1 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:QFP, QFP128,1.2SQ,32Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.61
Is Samacsys:NJESD-30 代码:S-PQFP-G128
JESD-609代码:e3长度:28 mm
湿度敏感等级:3功能数量:1
端子数量:128最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP128,1.2SQ,32
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:4.1 mm
子类别:Other Telecom ICs标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:DIGITAL TIME SWITCH温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:28 mm
Base Number Matches:1

MT90863AL1 数据手册

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MT90863  
3 V Rate Conversion Digital Switch  
Data Sheet  
September 2011  
Features  
2,048 512 and 512 x 512 switching among  
Ordering Information  
backplane and local streams  
MT90863AG  
MT90863AL1  
MT90863AG2  
144 Pin PBGA  
Trays  
128 Pin MQFP* Tubes  
Rate conversion between 2.048, 4.096 and  
8.192 Mb/s  
144 Pin PBGA** Trays, Bake & Drypack  
*Pb Free Matte Tin  
**Pb Free Tin/Silver/Copper  
Optional sub-rate switch configuration for  
2.048 Mb/s streams  
-40C to +85C  
Per-channel variable or constant throughput  
delay  
Compatible to HMVIP and H.100 specifications  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel message mode  
Applications  
Medium and large switching platforms  
CTI application  
Voice/data multiplexer  
Per-channel direction control  
Support ST-BUS, HMVIP and H.100 interfaces  
Per-channel high impedance output control  
Non-multiplexed microprocessor interface  
Connection memory block programming  
3.3 V local I/O with 5 V tolerant inputs and  
TTL-compatible outputs  
IEEE-1149.1 (JTAG) Test Port  
ODE  
ODE  
V
V
SS  
DD  
STio0/  
FEi0  
STo0  
Local  
Output  
Mux  
Multiple Buffer  
Data Memory  
(2,048 channels)  
STio15/  
FEi15  
Interface  
STo11  
STo12  
STo13  
Backplane  
Interface  
P/S  
Converter  
STio16/  
FEi16  
STo15  
Multiple Buffer  
Local  
STio23/  
FEi23  
S/P  
&
P/S  
Data Memory  
Internal  
Registers  
Connection  
Memory High/Low  
(512 locations)  
(512 channels)  
STi0  
STio24  
Local  
Interface  
Converter  
STi11  
STi12  
STi13  
Multiple Buffer  
Data Memory  
(512 channels)  
STio31  
S/P  
Converter  
Backplane  
Connection  
Memory  
STi15  
C16i  
F0i  
(2,048 locations)  
Timing  
Unit  
RESET  
IC1  
IC2  
C4i/C8i  
Test Port  
Microprocessor Interface  
TMS TDi TDo TCK TRST  
F0o C4o  
DS CS R/W A7-A0 DTA D15-D0  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2011, Zarlink Semiconductor Inc. All Rights Reserved.  
 
 

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