Datasheet > MT90871AV

MT90871AV

更新时间： 2024-11-22 21:57:47

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		开关
页数	文件大小	规格书
65页	641K
描述
Flexible 8K Digital Switch (F8KDX)

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数据手册

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MT90871AV 数据手册

MT90871

Flexible 8K Digital Switch (F8KDX)

Data Sheet

December 2002

Features

•

8,192-channel x 8,192-channel non-blocking

Ordering Information

unidirectional switching. The Backplane and

Local inputs and outputs can be combined to

form a non-blocking switching matrix with 32

stream inputs and 32 stream outputs.

MT90871AV 196 Ball LBGA

-40C to +85C

•

4,096-channel x 4,096 channel non-blocking

Backplane to Local stream switch.

•

Per-stream channel and bit delay for Local input

streams.

4,096-channel x 4,096 channel non-blocking

Local to Backplane stream switch.

Per-stream channel and bit delay for Backplane

4,096-channel x 4,096 channel non-blocking

input streams.

Backplane input to Backplane output switch.

Per-stream advancement for Local output

streams.

4,096-channel x 4,096 channel non-blocking

Local input to Local output stream switch.

Per-stream advancement for Backplane output

Rate conversion on all data paths, Backplane to

Local, Local to Backplane, Backplane to

Backplane and Local to Local streams.

Backplane port accepts 16 ST-BUS streams with

data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s

or 16.384Mb/s in any combination.

Local port accepts 16 ST-BUS streams with data

rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or

16.384Mb/s, in any combination.

streams.

•

Constant throughput delay for frame integrity.

Per-channel high impedance output control for

•

Local and Backplane streams.

•

Per-channel driven-high output control for Local

and Backplane streams.

High impedance-control outputs for external

drivers on Backplane and Local port.

SS (GND)

DD_IO

DD_CORE

RESET

ODE

Backplane Data Memories

(4,096 channels)

Local

BSTi0-15

BSTo0-15

LSTi0-15

Interface

Backplane

Local

Backplane

Interface

Connection Memory

(4,096 locations)

Connection Memory

(4,096 locations)

Interface

LSTo0-15

LCST0-1

BCST0-1

BORS

Local Data Memories

(4,096 channels)

LORS

FP8o

FP8i

Local

Backplane

FP16o

Timing

Unit

Timing Unit

C8o

C16o

Microprocessor Interface

and Internal Registers

Test Port

C8i

PLL

DD_PLL

DS CS R/W A14-A0 DTA D15-D0 TMS TDi TDo TCK TRST

Figure 1 - MT90871 Functional Block Diagram

Zarlink Semiconductor Inc.

12 3 4 5 6 7...65

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