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MT90863 PDF预览

MT90863

更新时间: 2024-11-23 04:14:11
品牌 Logo 应用领域
MITEL 开关
页数 文件大小 规格书
35页 156K
描述
3V Rate Conversion Digital Switch

MT90863 数据手册

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MT90863  
3V Rate Conversion Digital Switch  
Advance Information  
DS5034  
ISSUE 3  
March 1999  
Features  
2,048 × 512 and 512 x 512 switching among  
backplane and local streams  
Ordering Information  
Rate conversion between 2.048, 4.096 and  
8.192Mb/s  
MT90863AL1  
MT90863AG1  
128 Pin MQFP  
144 Pin BGA  
Optioal sub-rate switch configuration for  
2.048 Mb/s streams  
-40 to +85 C  
Per-channel variable or constant throughput  
delay  
Description  
Compatible to HMVIP and H.100 specifications  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel message mode  
The MT90863 Rate Conversion Switch provides  
switching capacities of 2,048 × 512 channels  
between backplane and local streams, and 512 x  
512 channels for local streams. The connected serial  
inputs and outputs may have 32, 64 and 128 64kb/s  
channels per frame with data rates of 2.048Mb/s,  
4.096Mb/s and 8.192Mb/s respectively.  
Per-channel direction control  
Per-channel high impedance output control  
Non-multiplexed microprocessor interface  
Connection memory block programming  
3.3V local I/O with 5V tolerant inputs and  
TTL-compatible outputs  
The MT90863 also offers a sub-rate switching  
configuration which allows 2-bit wide 16kb/s data  
channels to be switched within the device.  
IEEE-1149.1 (JTAG) Test Port  
Applications  
The device has features (such as: message mode;  
input and output offset delay; direction control; and,  
Medium and large switching platforms  
high  
impedance  
output  
control)  
that  
are  
CTI application  
programmable on per-stream or per-channel basis.  
Voice/data multiplexer  
Support ST-BUS, HMVIP and H.100 interfaces  
ODE  
ODE  
V
V
SS  
DD  
STio0/  
FEi0  
STo0  
Local  
Output  
Mux  
Multiple Buffer  
Data Memory  
(2,048 channels)  
STio15/  
FEi15  
Interface  
STo11  
STo12  
STo13  
Backplane  
Interface  
P/S  
Converter  
STio16/  
FEi16  
STo15  
Multiple Buffer  
Data Memory  
(512 channels)  
Local  
STio23/  
FEi23  
S/P  
&
P/S  
Internal  
Registers  
Connection  
Memory High/Low  
(512 locations)  
STi0  
STio24  
Local  
Interface  
Converter  
STi11  
STi12  
STi13  
Multiple Buffer  
Data Memory  
(512 channels)  
STio31  
S/P  
Converter  
Backplane  
Connection  
Memory  
STi15  
C16i  
F0i  
(2,048 locations)  
Timing  
Unit  
RESET  
IC1  
IC2  
C4i/C8i  
Test Port  
Microprocessor Interface  
TMS TDI TDO TCK TRST  
F0o C4o  
DS CS R/W A7-A0 DTA D15-D0  
Figure 1 - Functional Block Diagram  
1

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