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MT90866 PDF预览

MT90866

更新时间: 2024-09-26 10:43:47
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MITEL /
页数 文件大小 规格书
6页 37K
描述
WAN Access Switch

MT90866 数据手册

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MT90866  
WAN Access Switch  
Product Brief  
DS5279  
ISSUE 2  
Feburary 2000  
Features  
Ordering Information  
3.3V operation with 5V tolerant inputs and I/O’s  
MT90866AL  
MT90866AG  
256 Pin LQFP  
240 Pin LBGA  
2,432 x 2,432 channel non-blocking switching  
among local streams  
4,096 x 2,432 channel blocking switching  
between backplane and local streams  
-40°C to +85°C  
2,048 x 2,048 channel non-blocking switching  
among backplane streams  
Applications  
Rate conversion between backplane and local  
streams  
Multi-service access platforms  
CTI applications  
Rate conversion among local streams  
Gateways, Integrated Access Devices  
Backplane interface accepts data rates of  
8.192Mb/s or 16.384Mb/s  
ST-BUS and H.110 interface applications  
Local interface accepts data rates of 2.048Mb/  
s, 4.096Mb/s or 8.192Mb/s  
Description  
Sub-rate switching (2 or 4 bits) configuration for  
local streams at a data rate of 2.048Mb/s  
The MT90866 Digital Switch provides switching  
capacities of 4,096 x 2,432 channels between  
backplane and local streams, 2,432  
Per-channel variable or constant throughput  
delay  
x
2,432  
channels among local streams and 2,048 x 2,048  
channels among backplane streams. The local  
connected serial inputs and outputs have 32, 64 and  
128 64kb/s channels per frame with data rates of  
2.048, 4.096 and 8.192Mb/s respectively. The  
backplane connected serial inputs and outputs have  
128 and 256 64kb/s channels per frame with data  
rates of 8.192 and 16.384Mb/s respectively.  
Fully compliant to H.110 Timing specifications  
Automatic frame offset delay measurement for  
backplane streams  
Per-stream input frame delay offset, up to 128  
bytes, programmable for local streams on a per  
quarter bit or per channel basis  
Per-stream output frame advancement,  
programmable for backplane and local streams  
The MT90866 also offers a sub-rate switching  
configuration which allows 2-bit wide 16kb/s or 4-bit  
wide 32kb/s data channels to be switched within the  
device.  
Per-channel direction control for backplane  
streams  
Per-channel message mode for backplane and  
local streams  
Per-channel high impedance output control for  
backplane and local streams  
The device has features that are programmable on  
per-stream or per-channel basis including message  
mode, input delay offset, output advancement offset,  
direction control and high impedance output control.  
Pseudo-Random Binary Sequence (PRBS)  
pattern generation and testing for backplane  
and local streams  
5V tolerant PCI driver on CT-Bus I/O’s  
Integrated PLL, compatible to Stratum 4  
Enhanced clock switching standard  
Non-multiplexed microprocessor interface  
Connection memory block programming for fast  
device initialization  
Tristate-control outputs for external drivers  
Conform to the mandatory requirements of the  
IEEE-1149.1 (JTAG) standard  
1

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