MT90840
Distributed Hyperchannel Switch
Data Sheet
ISSUE 3
July 2002
Features
•
Time slot interchange function between eight
Ordering Information
pairs of ST-BUS/GCI/MVIPä streams (512
channels) and parallel data port
MT90840AL
100 Pin PQFP
MT90840AP 84 Pin PLCC
-40°C to 85°C
•
•
•
Programmable data rates on the parallel port
(19.44, 16.384, or 6.480 Mbyte/s)
Programmable data rates on the serial port (2.048
Mbps, 4.096 Mbps or 8.192 Mbps)
•
•
Diagnostic alarm functions and clock
phase-status word for clock monitoring
Supports star and point-to-point connections, and
unidirectional or bidirectional ring topologies for
distributed systems
IEEE 1149 (JTAG) boundary scan port
Applications
•
•
•
Input-to-output bypass function on the parallel
data port for use in add/drop applications
Bridging ST-BUS/MVIP buses to high speed
Time Division Multiplexed backplanes at
SONET rates (STS-1, STS-3)
Provides elastic buffer at parallel input port in the
receive direction
•
•
High speed isochronous backbones for
distributed PBX and LAN systems
•
•
Provides byte switching for up to 2430 channels
Per-channel direction control on the serial port
side
Switch platforms of up to 2430 channels with
guaranteed frame integrity for wideband
channels
•
•
•
•
Per-channel message mode and high-impedance
control on both parallel and serial port sides
•
•
•
Serial bus control and monitoring
Data multiplexing
8-bit multiplexed microprocessor port compatible
with Intel and Motorola microcontrollers
High speed communications interface
Guarantees frame integrity when switching nX64
wideband channels such as ISDN H0 channel
Provides external control lines allowing fast
parallel interface to be shared with other devices
STi0
STi7
Serial
to
8
Bidirectional
I/O
Driver
Multiple Pages of 512 Position
TX Path Data Memory
8
PDo0
PDo7
Output
Mux &
Drivers
Parallel
&
16
2430 Position
TX Path
Connection Memory
4
CTo0-3
PDi0
Parallel
to
Serial
8
STo0
STo7
Bidirectional
I/O
Driver
8
Multiple Pages of 2430-Byte
RX Path Data Memory
8
PDi7
Conver-
ters
15
512 Position
RX Path
PCKR
PCKT
RES
PPFRi
PPFTi/o
F0i/o
5
JTAG
TEST
Pins
Timing
Connection Memory
Control
Unit
Internal
Registers
CPU Interface
8
8
Figure 1 - Functional Block Diagram