Datasheet > MS81V04166A

MS81V04166A

更新时间： 2024-09-26 10:46:19

品牌	Logo	应用领域
冲电气 - OKI		先进先出芯片
页数	文件大小	规格书
19页	144K
描述
Dual FIFO (262,214 Words × 8 Bits) × 2

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MS81V04166A 数据手册

FEDS81V04166A-01

This version: Nov.,21, 2002

OKI Semiconductor

MS81V04166A

Dual FIFO (262,214 Words × 8 Bits) × 2

GENERAL DESCRIPTION

The MS81V04166A is a single-chip 4Mb FIFO functionally composed of two Oki’s 2Mb FIFO (First-In

First-Out) memories which were designed for 256k × 8-bit high-speed asynchronous read/write operation.

The read clock of each of the 2Mb FIFO memories is connected in common, and the clocks are provided

independently of each of the FIFO memories. The MS81V04166A functionally compatible with Oki’s 2Mb FIFO

memory (MSM51V8222A), can be used as a ×16 configuration FIFO.

The MS81V04166A is a field memory for wide or low end use in general commodity TVs and VTRs exclusively

and is not designed for high end use in professional graphics systems, which require long term picture storage, data

storage, medical use and other storage systems.

The MS81V04166A provides independent control clocks to support asynchronous read and write operations.

Different clock rates are also supported, which allow alternate data rates between write and read data streams.

The MS81V04166A provides high speed FIFO (First-in First-out) operation without external refreshing:

MS81V04166A refreshes its DRAM storage cells automatically, so that it appears fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access

operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the

power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration

logic.

The MS81V04166A’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set

by reset timing. The delay length and the number of read delay clocks between write and read, is determined by

externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers for the initial access of 71 × 16-bit enable high speed

first-bit-access with no clock delay just after the write or read reset timings.

The MS81V04166A, which is provided with two sets of the serial write clocks, allows the split-screen processing

to be implemented easily.

Additionally, the MS81V04166A has a write mask function or input enable function (IE), and read-data skipping

function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and

between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address

increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to the

MS81V04166A. The input enable (IE) function allows the user to write into selected locations of the memory only,

leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in picture”

on a TV screen.

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与MS81V04166A相关器件

型号	品牌	获取价格	描述	数据表
MS81V04166A-20TB	OKI	获取价格	FIFO, 256KX8, 18ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
MS81V04166A-25TB	OKI	获取价格	FIFO, 256KX8, 23ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
MS81V04166A-XXTB	OKI	获取价格	Dual FIFO (262,214 Words 】 8 Bits) 】 2
MS81V04166-XXTB	OKI	获取价格	Dual FIFO (262,214 Words × 8 Bits) × 2
MS81V05200	OKI	获取价格	(583,680-word × 10-bit) FIFO memory
MS81V05200-TA	OKI	获取价格	暂无描述
MS81V06160	OKI	获取价格	(401,408-word ⅴ 16-bit) FIFO memory
MS81V06160-15TA	OKI	获取价格	FIFO, 392KX16, 12ns, Asynchronous, CMOS, PDSO70, 0.400 INCH, 0.50 MM PITCH, PLASTIC, TSOP2
MS81V10160	OKI	获取价格	(664,320-word x 16-bit) FIFO memory
MS81V26000	OKI	获取价格	1,114,112-Word X 24-Bit Field Memory

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