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MPC9850VF PDF预览

MPC9850VF

更新时间: 2024-11-11 10:49:15
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 晶体时钟发生器外围集成电路
页数 文件大小 规格书
12页 244K
描述
Clock Generator for PowerQUICC III

MPC9850VF 数据手册

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MPC9850  
Rev 5, 4/2005  
Freescale Semiconductor  
Technical Data  
Clock Generator for PowerQUICC III  
MPC9850  
The MPC9850 is a PLL based clock generator specifically designed for  
Freescale Microprocessor and Microcontroller applications including the  
PowerQUICC III. This device generates a microprocessor input clock plus the  
500 MHz Rapid I/O clock. The microprocessor clock is selectable in output  
frequency to any of the commonly used microprocessor input and bus  
frequencies. The Rapid I/O outputs are LVDS compatible. The device offers eight  
low skew clock outputs organized into two output banks, each configurable to  
support different clock frequencies. The extended temperature range of the  
MPC9850 supports telecommunication and networking requirements.  
MICROPROCESSOR  
CLOCK GENERATOR  
Features  
8 LVCMOS outputs for processor and other circuitry  
2 differential LVDS outputs for Rapid I/O interface  
Crystal oscillator or external reference input  
25 or 33 MHz Input reference frequency  
Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,  
50, 33 or 16 MHz  
VF SUFFIX  
VM SUFFIX (PB-FREE)  
100 MAPBGA PACKAGE  
CASE 1462-01  
Buffered reference clock output  
Rapid I/O (LVDS) Output = 500, 250 or 125 MHz  
Low cycle-to-cycle and period jitter  
100-lead PBGA package  
100-lead Pb-free Package Available  
3.3V supply with 3.3V or 2.5V output LVCMOS drive  
Supports computing, networking, telecommunications applications  
Ambient temperature range –40°C to +85°C  
Functional Description  
The MPC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency  
is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers,  
divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111,  
100, 83 66 50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use  
in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency  
is also divided to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III  
communications processor. The input reference, either crystal or external input is also buffered to a separate output that my be  
used as the clock source for a Gigabit Ethernet PHY if desired.  
The reference clock may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a  
25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and  
selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal  
oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are  
required for crystal oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input  
frequency.  
The MPC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  

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