5秒后页面跳转
MPC991 PDF预览

MPC991

更新时间: 2024-11-10 22:28:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟驱动器
页数 文件大小 规格书
9页 150K
描述
LOW VOLTAGE PLL CLOCK DRIVER

MPC991 数据手册

 浏览型号MPC991的Datasheet PDF文件第2页浏览型号MPC991的Datasheet PDF文件第3页浏览型号MPC991的Datasheet PDF文件第4页浏览型号MPC991的Datasheet PDF文件第5页浏览型号MPC991的Datasheet PDF文件第6页浏览型号MPC991的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MPC990/991 is a 3.3V compatible, PLL based ECL/PECL clock  
driver. The fully differential design ensures optimum skew and PLL jitter  
performance. The performance of the MPC990/991 makes the device  
ideal for Workstation, Mainframe Computer and Telecommunication  
applications. The MPC990 and MPC991 devices are identical except in  
the interface to the reference clock for the PLL. The MPC990 offers an  
on–board crystal oscillator as the PLL reference while the MPC991 offers  
a differential ECL/PECL input for applications which need to lock to an  
existing clock signal. Both designs offer a secondary single–ended ECL  
clock for system test capabilities.  
LOW VOLTAGE  
PLL CLOCK DRIVER  
Fully Integrated PLL  
Output Frequency Up to 400MHz  
ECL/PECL Inputs and Outputs  
Operates from a 3.3V Supply  
Output Frequency Configurable  
TQFP Packaging  
±50ps Cycle–to–Cycle Jitter  
The MPC990/991 offers three banks of outputs which can each be  
programmed via the the four fsel pins of the device. There are 16 different  
output frequency configurations available in the device. The  
configurations include output ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and  
4:3:2. The programming table in this data sheet illustrates the various  
programming options. The SYNC output monitors the relationship  
between the Qa and Qc output banks. The output pulses per the timing  
diagrams in this data sheet signal the coincident edges of the two output  
FA SUFFIX  
52–LEAD TQFP PACKAGE  
CASE 848D–03  
banks. This feature is useful for non binary relationships between output frequencies (i.e., 3:2 or 4:3 relationships). The Sync_Sel  
input toggles the Qd outputs between sync signals and extensions to the Qc bank of outputs.  
The MPC990/991 provides a separate output for the feedback to the PLL. This allows for the feedback frequency to be  
programmed independently of the other outputs allowing for unique input vs output frequency relationships. The fselFB inputs  
provide 6 different feedback frequencies from the QFB differential output pair.  
The MPC990/991 features an external differential ECL/PECL feedback to the PLL. This external feedback feature allows for  
the MPC991’s use as a “zero” delay buffer. The propagation delay between the input reference and the output is dependent on  
the input reference frequency. The selection of higher reference frequencies will provide near zero delay through the device.  
The PLL_En, Ref_Sel and the Test_Clk input pins provide a means of bypassing the PLL and driving the output buffers  
directly. This allows the user to single step a design during system debug. Note that the Test_Clk input is routed through the  
dividers so that depending on the programming several edges on the Test_Clk input will be needed to get corresponding edge  
transitions on the outputs. The VCO_Sel input provides a means of recentering the VCO to provide a broader range of VCO  
frequencies for stable PLL operation.  
If the frequency select or the VCO_Sel pins are changed during operation, a master reset signal must be applied to ensure  
output synchronization and phase–lock. If the VCO is driven beyond its maximum frequency, the VCO can outrun the internal  
dividers when the VCO_Sel pin is low. This will also prevent the PLL from achieving lock. Again, a master reset signal will need to  
be applied to allow for phase–lock. The device employs a power–on reset circuit which will ensure output synchronization and  
PLL lock on initial power–up.  
2/97  
REV 2  
Motorola, Inc. 1997  

与MPC991相关器件

型号 品牌 获取价格 描述 数据表
MPC991FAR2 MOTOROLA

获取价格

ECL SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, TQFP-
MPC992 MOTOROLA

获取价格

LOW VOLTAGE PLL CLOCK DRIVER
MPC992FA NXP

获取价格

375MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32, LQFP-32
MPC992FA MOTOROLA

获取价格

Clock Generator, 375MHz, CMOS, PQFP32, PLASTIC, TQFP-32
MPC992FA IDT

获取价格

Clock Generator, 375MHz, PQFP32, LQFP-32
MPC993 MOTOROLA

获取价格

Dynamic Switch PLL Clock Driver
MPC993FA NXP

获取价格

IC,1:5 OUTPUT, DIFFERENTIAL,CMOS,QFP,32PIN,PLASTIC
MPC993FA MOTOROLA

获取价格

PLL Based Clock Driver, MPC900 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PQFP3
MPC993FAR2 MOTOROLA

获取价格

MPC900 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLA
MPC9952FA NXP

获取价格

IC,1:11 OUTPUT,QFP,32PIN,PLASTIC