Datasheet > MPC9990FA

MPC9990FA

更新时间： 2024-11-11 14:34:47

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
12页	371K
描述
PLL Based Clock Driver, 9990 Series, 10 True Output(s), 0 Inverted Output(s), PQFP48, LQFP-48

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MPC9990FA 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	48
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.47	Is Samacsys：	N
系列：	9990	输入调节：	DIFFERENTIAL
JESD-30 代码：	S-PQFP-G48	JESD-609代码：	e0
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	48	实输出次数：	10
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	240	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.25 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	7 mm	最小 fmax：	287.5 MHz
Base Number Matches：	1

MPC9990FA 数据手册

Order Number: MPC9990/D

DATA SHEET

Rev 5, 03/2002

SEMICONDUCTOR TECHNICAL DATA

MPC9990

Low Voltage PLL Clock Driver

The MPC9990 is a low voltage PLL clock driver designed for high

speed clock generation and distribution in high performance computer,

workstation and server applications. The clock driver accepts a LVPECL

compatible clock signal and provides 10 low skew, differential HSTL

compatible outputs, one HSTL compatible output for system

synchronization purposes and one HSTL compatible PLL feedback

output. The device operates from a dual voltage supply: 3.3 V for the core

logic and 1.8 V for the HSTL outputs. The fully integrated PLL supports an

input frequency range of 75 to 287.5 MHz. The output frequencies are

configurable.

LOW VOLTAGE

DIFFERENTIAL PECL–HSTL

PLL CLOCK DRIVER

• Supports high performance HSTL clock distribution systems

• Compatible to IA64 processor systems

• Fully Integrated PLL, differential design

• Core logic operates from 3.3 V power supply

• HSTL outputs operate from a 1.8 V supply

• Programmable frequency by output bank

• 10 HSTL compatible outputs (two banks)

• HSTL compatible PLL feedback output

• HSTL compatible sychronization output (QSYNC)

• Max. skew of 80 ps within output bank

FA SUFFIX

48–LEAD LQFP PACKAGE

CASE 932

• Zero–delay capability: max. SPO (tpd) window of 150 ps

• LVPECL compatible clock input, LVCMOS compatible control inputs

• Temperature range of 0 to +70°C

The MPC9990 provides output clock frequencies required for high–performance computer system optimization. The device

drives up to 10 differential clock loads within the frequency range of 75 to 287.5 MHz. The 10 outputs are organized in 2 banks of

3 and 7 differential outputs. In the standard configuration the QFB output pair is connected to the FB input pair closing the PLL

loop and enabling zero delay operation from the CLK input to the outputs. Bank B outputs are frequency and phase aligned to the

CLK input, providing exact copies of the high–speed input signal. Bank A outputs are configured to operate at slower speeds

driving the system bus devices. The output frequency ratio of bank A to bank B is adjustable (for available ratios, see “MPC9990

Application: CPU to System Bus Frequency Ratios” on page 2) for system optimization. In a computer application, bank B

outputs generate the clock signals for the devices operating at the CPU frequency, while Bank A outputs are configured to drive

the clock signals for the devices running at lower speeds (system clock). Four individual frequency ratios are available, providing

a high degree of flexibility. The frequency ratios between CPU clock and system clock provided by the MPC9990 are listed in the

table “Output configuration” on page 4.

The QSYNC output functionality is designed for system synchronization purpose. QSYNC is asserted at coincident rising

edges of CPU (bank B and QFB signal) and slower system clock (bank A) outputs (see “QSYNC Phase Relation Diagram” on

page 4), providing baseline timing in systems with fractional clocks. The QSYNC output is asserted for one QFB high pulse,

centered on the rising QFB output.

CLK

QB[0:2]

QA[0:6]

QSYNC

CPU clocks

250 MHz

System clocks: 250, 200,

187, 125 MHz

System synchronization

QFB

MPC9990

250 MHz

Figure 1. MPC9990 Application Example

1. In order to minimize output–to–output skew, HSTL outputs of the MPC9990 are generated with an open emitter architecture. For output

termination, see ”HSTL Output Termination and AC Test Reference” on page 5.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

IDT™ Low Voltage PLL Clock Driver

MPC9990

Motorola, Inc. 2002

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

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与MPC9990FA相关器件

型号	品牌	获取价格	描述	数据表
MPC9990FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, PLASTIC, LQFP-48
MPC9992	MOTOROLA	获取价格	3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR
MPC9992AC	IDT	获取价格	Clock Generator, 400MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-02
MPC9992AC	NXP	获取价格	400MHz, OTHER CLOCK GENERATOR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BBA, LQF
MPC9992ACR2	IDT	获取价格	Clock Generator, 400MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BBA, LQFP-32
MPC9992FA	MOTOROLA	获取价格	400 MHz, OTHER CLOCK GENERATOR, PQFP32, LQFP-32
MPC9992FA	NXP	获取价格	IC,MISCELLANEOUS CLOCK GENERATOR,QFP,32PIN,PLASTIC
MPC9992FA	IDT	获取价格	Clock Generator, 400MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-
MPC9992FAR2	MOTOROLA	获取价格	Clock Generator, 400MHz, CMOS, PQFP32, LQFP-32
MPC9993	MOTOROLA	获取价格	INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER

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