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MPC9993FAR2 PDF预览

MPC9993FAR2

更新时间: 2024-11-11 21:16:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动输出元件
页数 文件大小 规格书
7页 97K
描述
PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32

MPC9993FAR2 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.27输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:5最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.08 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:7 mm最小 fmax:100 MHz
Base Number Matches:1

MPC9993FAR2 数据手册

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ꢀꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ  
SEMICONDUCTOR TECHNICAL DATA  
Order Number: MPC9993/D  
Rev 1, 04/2003  
ꢇꢈ ꢍꢎꢇ ꢏ ꢐ ꢋꢑ ꢒꢊ ꢓꢑ ꢔ  
ꢆꢍꢒ ꢕ ꢙ ꢚꢄ ꢄ ꢒꢊꢓꢑ ꢔ  
The MPC9993 is a PLL clock driver designed specifically for redundant  
clock tree designs. The device receives two differential LVPECL clock  
signals from which it generates 5 new differential LVPECL clock outputs.  
Two of the output pairs regenerate the input signals frequency and phase  
while the other three pairs generate 2x, phase aligned clock outputs.  
Features:  
3
Fully Integrated PLL  
FA SUFFIX  
32–LEAD LQFP PACKAGE  
CASE 873A  
Intelligent Dynamic Clock Switch  
LVPECL Clock Outputs  
LVCMOS Control I/O  
3.3V Operation  
32–Lead LQFP Packaging  
Functional Description  
The MPC9993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection  
of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary  
clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase  
disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).  
ꢌ ꢥ  
ꢒꢥ  
ꢒꢥ  
ꢥ ꢌ  
÷
÷ꢄ  
Figure 1. Block Diagram  
362  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  

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