Datasheet > MPC9992FA

MPC9992FA

更新时间： 2024-11-11 21:14:39

品牌	Logo	应用领域
恩智浦 - NXP		时钟局域网外围集成电路晶体
页数	文件大小	规格书
12页	313K
描述
IC,MISCELLANEOUS CLOCK GENERATOR,QFP,32PIN,PLASTIC

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MPC9992FA 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32
针数：	32	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.22	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e0	长度：	7 mm
湿度敏感等级：	2	端子数量：	32
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	400 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP32,.35SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	220	电源：	3.3 V
主时钟/晶体标称频率：	400 MHz	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Clock Generators
最大压摆率：	1 mA	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	7 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

MPC9992FA 数据手册

MPC9992

Rev 5, 06/2005

Freescale Semiconductor

Technical Data

3.3 V Differential ECL/PECL PLL

Clock Generator

MPC9992

The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using

SiGe technology and a fully differential design ensures optimum skew and PLL

jitter performance. The performance of the MPC9992 makes the device ideal for

workstation, mainframe computer and telecommunication applications. With

output frequencies up to 400 MHz and output skews less than 100 ps the device

meets the needs of the most demanding clock applications. The MPC9992 offers

a differential PECL input and a crystal oscillator interface. All control signals are

LVCMOS compatible.

3.3 V DIFFERENTIAL

ECL/PECL

CLOCK GENERATOR

Features

•

7 differential outputs, PLL based clock generator

SiGe technology supports minimum output skew (max. 100 ps)

Supports up to two generated output clock frequencies with a maximum clock

frequency up to 400 MHz

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-04

•

Selectable crystal oscillator interface and PECL compatible clock input

SYNC pulse generation

PECL compatible differential clock inputs and outputs

Single 3.3 V (PECL) supply

Ambient temperature range 0°C to +70°C

Standard 32 lead LQFP package

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-04

Pin and function compatible to the MPC992

32-lead Pb-free Package Available

Functional Description

The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock fre-

quency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency

range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input

relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback fre-

quency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input ref-

erence frequency range.

The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC gen-

erator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between

output frequencies.

The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock sig-

nal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input

reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock

frequency specification and all other PLL characteristics do not apply.

The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted.

Assertion of the reset signal forces all outputs to the logic low state.

The MPC9992 is fully 3.3 V compatible and requires no external loop filter components. The differential clock input (PCLK) is

PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels

with the capability to drive terminated 50 Ω transmission lines.

The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package.

12 3 4 5 6 7...12

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与MPC9992FA相关器件

型号	品牌	获取价格	描述	数据表
MPC9992FAR2	MOTOROLA	获取价格	Clock Generator, 400MHz, CMOS, PQFP32, LQFP-32
MPC9993	MOTOROLA	获取价格	INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER
MPC9993AC	IDT	获取价格	PLL Based Clock Driver, 9993 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC9993ACR2	IDT	获取价格	PLL Based Clock Driver, 9993 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC9993D	MOTOROLA	获取价格	INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER
MPC9993DFA	MOTOROLA	获取价格	INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER
MPC9993FA	MOTOROLA	获取价格	INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER
MPC9993FAR2	NXP	获取价格	IC,1:5 OUTPUT, DIFFERENTIAL,CMOS,QFP,32PIN,PLASTIC
MPC9993FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32
MPC99J93	MOTOROLA	获取价格	Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver

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