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MPC9952FA PDF预览

MPC9952FA

更新时间: 2024-11-11 19:31:07
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
5页 270K
描述
IC,1:11 OUTPUT,QFP,32PIN,PLASTIC

MPC9952FA 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:9952
输入调节:STANDARDJESD-30 代码:S-PQFP-G32
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:11
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.55 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:7 mm最小 fmax:180 MHz
Base Number Matches:1

MPC9952FA 数据手册

 浏览型号MPC9952FA的Datasheet PDF文件第2页浏览型号MPC9952FA的Datasheet PDF文件第3页浏览型号MPC9952FA的Datasheet PDF文件第4页浏览型号MPC9952FA的Datasheet PDF文件第5页 
Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MPC9952/D  
ꢀꢎ ꢏꢖ ꢖꢗ ꢘ  
See Upgrade Product – MPC9352  
The MPC9952 is a 3.3V compatible, PLL based clock driver device  
targeted for high performance clock tree applications. The device fea-  
tures a fully integrated PLL with no external components required. With  
output frequencies of up to 180MHz and eleven low skew outputs the  
MPC9952 is well suited for high performance designs. The device em-  
ploys a fully differential PLL design to optimize jitter and noise rejection  
performance. Jitter is an increasingly important parameter as more micro-  
processors and ASiC’s are employing on chip PLL clock distribution.  
2
LOW VOLTAGE  
PLL CLOCK DRIVER  
Fully Integrated PLL  
Output Frequency up to 180MHz  
High Impedance Disabled Outputs  
Compatible with PowerPC, Intel and High Performance RISC Micro-  
processors  
Output Frequency Configurable  
LQFP Packaging  
100ps Cycle–to–Cycle Jitter  
The MPC9952 features three banks of individually configurable out-  
puts. The banks contain 5 outputs, 4 outputs and 2 outputs. The internal  
divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1.  
The output frequency relationship is controlled by the fsel frequency con-  
trol pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL  
compatible inputs.  
FA SUFFIX  
LQFP PACKAGE  
CASE 873A-02  
The MPC9952 uses external feedback to the PLL. This features allows  
for the use of the device as a “zero delay” buffer. Any of the  
eleven outputs can be used as the feedback to the PLL. The VCO_Sel  
pin allows for the choice of two VCO ranges to optimize PLL stability and  
jitter performance. The MR/OE pin allows the user to force the outputs  
into high impedance for board level test.  
For system debug the PLL of the MPC9952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the  
signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it  
may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the  
design for debug purposes.  
The outputs of the MPC9952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines.  
For applications using series terminated transmission lines each MPC9952 output can drive two lines. This capability provides an  
effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines  
consult the applications section of this data sheet.  
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.  
Rev 2  
282  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  
For More Information On This Product,  
Go to: www.freescale.com  

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