MPC9893FA

更新时间： 2024-11-12 13:11:47

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		分布式控制系统 DCS 时钟
页数	文件大小	规格书
16页	475K
描述
PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, LQFP-48

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MPC9893FA 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	LFQFP, QFP48,.35SQ,20	针数：	48
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.24	其他特性：	ALSO OPERATES AT 3.3V SUPPLY
输入调节：	MUX	JESD-30 代码：	S-PQFP-G48
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	48	实输出次数：	12
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.1 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	2.625 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	7 mm	最小 fmax：	60 MHz
Base Number Matches：	1

MPC9893FA 数据手册

MOTOROLA

Document Number: MPC9893/D

Rev 3, 01/2004

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Low Voltage PLL Intelligent

Dynamic Clock (IDCS) Switch

MPC9893

The MPC9893 is a 2.5V and 3.3V compatible, PLL based intelligent

dynamic clock switch and generator specifically designed for redundant

clock distribution systems. The device receives two LVCMOS clock

signals and generates 12 phase aligned output clocks. The MPC9893 is

able to detect a failing reference clock signal and to dynamically switch to

a redundant clock signal. The switch from the failing clock to the

redundant clock occurs without interruption of the output clock signal

(output clock slews to alignment). The phase bump typically caused by a

clock failure is eliminated.

LOW VOLTAGE 2.5V AND 3.3V

IDCS AND PLL

CLOCK GENERATOR

The device offers 12 low skew clock outputs organized into two output

banks, each configurable to support the different clock frequencies.

The extended temperature range of the MPC9893 supports

telecommunication and networking requirements. The device employs a

fully differential PLL design to minimize jitter.

Features

• 12 output LVCMOS PLL clock generator

• 2.5V and 3.3V compatible

FA SUFFIX

48--LEAD LQFP PACKAGE

CASE 932

• IDCS - on-chip intelligent dynamic clock switch

• Automatically detects clock failure

• Smooth output phase transition during clock failover switch

• 7.5 - 200 MHz output frequency range

• LVCMOS compatible inputs and outputs

• External feedback enables zero-delay configurations

• Supports networking, telecommunications and computer applications

• Output enable/disable and static test mode (PLL bypass)

• Low skew characteristics: maximum 50 ps output-to-output (within bank)

• 48 lead LQFP package

• Ambient operating temperature range of --40 to 85°C

Functional Description

The MPC9893 is a 3.3V or 2.5V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated

PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two,

three, four or eight. The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same

frequency than bank A or at half of the bank A frequency. Therefore, bank B outputs additionally support the frequency

multiplication of the input reference clock by 3÷2 and 1÷2. Bank A and bank B outputs are phase-aligned . Due to the external

PLL feedback, the clock signals of both output banks are also phase-aligned to the selected input reference clock, providing

virtually zero-delay capability. The integrated IDCS continuously monitors both clock inputs and indicates a clock failure

individually for each clock input. When a false clock signal is detected, the MPC9893 switches to the redundant clock input,

forcing the PLL to slowly slew to alignment and not produce any phase bumps at the outputs. Both clock inputs are

interchangeable, also supporting the switch to a failed clock that was restored. The MPC9893 also provides a manual mode that

allows for user-controlled clock switches.

The PLL bypass of the MPC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the

MPC9893 is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9893 can be

disabled (high-impedance tristate) to isolate the device from the system. Applying output disable also resets the MPC9893. On

power-up this reset function needs to be applied for correct operation of the circuitry. Please see the application section for

power-on sequence recommendations.

The device is packaged in a 7x7 mm 48-lead LQFP package.

1. At coincident rising edges

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...16

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与MPC9893FA相关器件

型号	品牌	获取价格	描述	数据表
MPC9893FAR2	IDT	获取价格	PLL Based Clock Driver, 9893 Series, 12 True Output(s), 0 Inverted Output(s), CMOS, PQFP48
MPC9894	ETC	获取价格	Quad Input Redundant IDCS Clock Generator
MPC9894VF	NXP	获取价格	9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100, 11 X
MPC9894VF	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100, 11 X 11 MM, MAPBG
MPC9894VFR2	NXP	获取价格	PLL Based Clock Driver, 9894 Series, 8 True Output(s), 0 Inverted Output(s), PBGA100, 11 X
MPC9894VM	IDT	获取价格	PLL Based Clock Driver, 9894 Series, 8 True Output(s), 0 Inverted Output(s), PBGA100, 11 X
MPC990	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC990FA	MOTOROLA	获取价格	400MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, PLASTIC, TQFP-52
MPC990FAR2	MOTOROLA	获取价格	400MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, TQFP-52
MPC991	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER

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