5秒后页面跳转
MPC9894 PDF预览

MPC9894

更新时间: 2024-11-10 22:51:11
品牌 Logo 应用领域
其他 - ETC 时钟发生器分布式控制系统DCS
页数 文件大小 规格书
28页 367K
描述
Quad Input Redundant IDCS Clock Generator

MPC9894 数据手册

 浏览型号MPC9894的Datasheet PDF文件第2页浏览型号MPC9894的Datasheet PDF文件第3页浏览型号MPC9894的Datasheet PDF文件第4页浏览型号MPC9894的Datasheet PDF文件第5页浏览型号MPC9894的Datasheet PDF文件第6页浏览型号MPC9894的Datasheet PDF文件第7页 
MPC9894  
Rev 3, 1/2005  
Freescale Semiconductor  
Technical Data  
Quad Input Redundant IDCS Clock  
Generator  
MPC9894  
The MPC9894 is a differential input and output, PLL-based Intelligent  
Dynamic Clock Switch (IDCS) and clock generator specifically designed for  
redundant clock distribution systems. The device receives up to four LVPECL  
clock signals and generates eight phase-aligned output clocks. The MPC9894 is  
able to detect failing clock signals and to dynamically switch to a redundant clock  
signal. The switch from the failing clock to the redundant clock occurs without  
interruption of the output clock signal (output clock slews to alignment). The  
phase bump typically caused by a clock failure is eliminated. The device offers  
eight low-skew clock outputs organized into four output banks, each configurable  
to support the different clock frequencies. The extended temperature range of  
the MPC9894 supports telecommunication and networking requirements.  
QUAD INPUT REDUNDANT  
IDCS CLOCK GENERATOR  
Features  
8 differential LVPECL output pairs  
Quad-redundancy reference clock inputs  
IDCS-on-chip intelligent dynamic clock switch  
Smooth output phase transition during clock failover switch/*  
Automatically detects clock failures  
Clock activity monitor  
Clock qualifier inputs  
Manual clock select and automatic switch modes  
21.25 – 340 MHz output frequency range  
Specified frequency and phase slew rate on clock switch  
LVCMOS compatible control inputs and outputs  
External feedback enables zero-delay configurations  
Output enable/disable and static test mode (PLL bypass)  
Low-skew characteristics: maximum 50 ps(1) output-to-output  
I2C interface for device configuration  
VF SUFFIX  
100-LEAD MAPBGA PACKAGE  
CASE 1462-01  
Low cycle-to-cycle and period jitter  
IEEE 1149.1 JTAG Interface  
100-ball MAPBGA package  
Supports 2.5 V or 3.3 V supplies with 2.5 V and 3.3 V I/O  
Junction temperature range –40°C to +110°C  
Functional Description  
The MPC9894 is a quad differential redundant input clock generator. The device contains logic for clock failure detection and  
auto switching for clock redundant applications. The generator uses a fully integrated PLL to generate clock signals from any one  
of four redundant clock sources. The PLL multiplies the frequency of the input reference clock by one, two, four, eight or divides  
the reference clock by two or four. The frequency-multiplied clock signal drives four banks of two differential outputs. Each bank  
allows an individual frequency-divider configuration. All outputs are phase-aligned(1) to each other. Due to the external PLL  
feedback, the clock signals of all outputs are also phase-aligned(1) to the selected input reference clock, providing virtually  
zero-delay capability.  
The integrated IDCS continuously monitors all four clock inputs and indicates a clock failure for each clock input. When a false  
clock signal is detected on the active clock, the MPC9894 switches to a redundant clock input, forcing the PLL to slowly slew to  
alignment and not produce any phase bumps at the outputs. The MPC9894 also provides a manual mode that allows for  
user-controlled clock switches.  
The device is packaged in a 11x11 mm2 100-ball MAPBGA package.  
1. At coincident rising edges.  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  

与MPC9894相关器件

型号 品牌 获取价格 描述 数据表
MPC9894VF NXP

获取价格

9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100, 11 X
MPC9894VF MOTOROLA

获取价格

PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100, 11 X 11 MM, MAPBG
MPC9894VFR2 NXP

获取价格

PLL Based Clock Driver, 9894 Series, 8 True Output(s), 0 Inverted Output(s), PBGA100, 11 X
MPC9894VM IDT

获取价格

PLL Based Clock Driver, 9894 Series, 8 True Output(s), 0 Inverted Output(s), PBGA100, 11 X
MPC990 MOTOROLA

获取价格

LOW VOLTAGE PLL CLOCK DRIVER
MPC990FA MOTOROLA

获取价格

400MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, PLASTIC, TQFP-52
MPC990FAR2 MOTOROLA

获取价格

400MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, TQFP-52
MPC991 MOTOROLA

获取价格

LOW VOLTAGE PLL CLOCK DRIVER
MPC991FAR2 MOTOROLA

获取价格

ECL SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, TQFP-
MPC992 MOTOROLA

获取价格

LOW VOLTAGE PLL CLOCK DRIVER