Datasheet > MPC9894VF

MPC9894VF

更新时间： 2024-11-12 20:05:51

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		驱动输出元件逻辑集成电路
页数	文件大小	规格书
32页	337K
描述
PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100, 11 X 11 MM, MAPBGA-100

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MPC9894VF 技术参数

生命周期：	Transferred	零件包装代码：	BGA
包装说明：	LBGA, BGA100,10X10,40	针数：	100
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.27	其他特性：	ALSO OPERATES AT 3.3V SUPPLY
输入调节：	DIFFERENTIAL MUX	JESD-30 代码：	S-PBGA-B100
长度：	11 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	100	实输出次数：	8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.05 ns	座面最大高度：	1.7 mm
最大供电电压 (Vsup)：	2.625 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	11 mm
最小 fmax：	170 MHz	Base Number Matches：	1

MPC9894VF 数据手册

MOTOROLA

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by MPC9894/D

SEMICONDUCTOR TECHNICAL DATA

Preliminary Information

Quad Input Redundant IDCS Clock

Generator

MPC9894

The MPC9894 is a differential input and output, PLL-based Intelligent

Dynamic Clock Switch (IDCS) and clock generator specifically designed for

redundant clock distribution systems. The device receives up to four LVPECL

clock signals and generates eight phase-aligned output clocks. The

MPC9894 is able to detect failing clock signals and to dynamically switch to

a redundant clock signal. The switch from the failing clock to the redundant

clock occurs without interruption of the output clock signal (output clock slews

to alignment). The phase bump typically caused by a clock failure is eliminat-

ed. The device offers eight low-skew clock outputs organized into four output

banks, each configurable to support the different clock frequencies. The ex-

tended temperature range of the MPC9894 supports telecommunication and

networking requirements.

QUAD INPUT REDUNDANT

IDCS CLOCK GENERATOR

Features

• 8 differential LVPECL output pairs

• Quad-redundancy reference clock inputs

• IDCS-on-chip intelligent dynamic clock switch

• Smooth output phase transition during clock failover switch

• Automatically detects clock failures

VF SUFFIX

100-LEAD MAP BGA PACKAGE

CASE 1462

• Clock activity monitor

• Clock qualifier inputs

• Manual clock select and automatic switch modes

• 21.25 — 340 MHz output frequency range

• Specified frequency and phase slew rate on clock switch

• LVCMOS compatible control inputs and outputs

• External feedback enables zero-delay configurations

• Output enable/disable and static test mode (PLL bypass)

• low-skew characteristics: maximum 50 ps1 output-to-output

• I²C interface for device configuration

• Low cycle-to-cycle and period jitter

• IEEE 1149.1 JTAG Interface

• 100-ball MAPBGA package

• Supports 2.5 V or 3.3 V supplies with 2.5 V and 3.3 V I/O

• Junction temperature range -40°C to +110°C

Functional Description

The MPC9894 is a quad differential redundant input clock generator. The device contains logic for clock failure detection and

auto switching for clock redundant applications. The generator uses a fully integrated PLL to generate clock signals from any one of

four redundant clock sources. The PLL multiplies the frequency of the input reference clock by one, two, four, eight or divides the

reference clock by two or four. The frequency-multiplied clock signal drives four banks of two differential outputs. Each bank allows

an individual frequency-divider configuration. All outputs are phase-aligned²to each other. Due to the external PLL feedback, the

clock signals of all outputs are also phase-aligned²to the selected input reference clock, providing virtually zero-delay capability.

The integrated IDCS continuously monitors all four clock inputs and indicates a clock failure for each clock input. When a false

clock signal is detected on the active clock, the MPC9894 switches to a redundant clock input, forcing the PLL to slowly slew to align-

ment and not produce any phase bumps at the outputs. The MPC9894 also provides a manual mode that allows for user-controlled

clock switches.

The device is packaged in a 11x11 mm²100-ball MAPBGA package.

1. Final specification subject to change.

2. At coincident rising edges.

REV 2

12 3 4 5 6 7...32

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与MPC9894VF相关器件

型号	品牌	获取价格	描述	数据表
MPC9894VFR2	NXP	获取价格	PLL Based Clock Driver, 9894 Series, 8 True Output(s), 0 Inverted Output(s), PBGA100, 11 X
MPC9894VM	IDT	获取价格	PLL Based Clock Driver, 9894 Series, 8 True Output(s), 0 Inverted Output(s), PBGA100, 11 X
MPC990	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC990FA	MOTOROLA	获取价格	400MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, PLASTIC, TQFP-52
MPC990FAR2	MOTOROLA	获取价格	400MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, TQFP-52
MPC991	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC991FAR2	MOTOROLA	获取价格	ECL SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, TQFP-
MPC992	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC992FA	NXP	获取价格	375MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32, LQFP-32
MPC992FA	MOTOROLA	获取价格	Clock Generator, 375MHz, CMOS, PQFP32, PLASTIC, TQFP-32

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