Datasheet > MPC990FAR2

MPC990FAR2

更新时间： 2024-11-12 19:58:47

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟外围集成电路晶体
页数	文件大小	规格书
12页	116K
描述
400MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52, TQFP-52

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MPC990FAR2 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP,
针数：	52	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	其他特性：	DIFFERENTIAL O/P'S
JESD-30 代码：	S-PQFP-G52	JESD-609代码：	e0
长度：	10 mm	端子数量：	52
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	400 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	NOT SPECIFIED
主时钟/晶体标称频率：	25 MHz	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	ECL
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

MPC990FAR2 数据手册

Order Number: MPC990/D

Rev 4, 09/2001

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SEMICONDUCTOR TECHNICAL DATA

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The MPC990 is a 3.3 V compatible, PLL based clock driver. The fully

differential design ensures optimum skew and PLL jitter performance. The

performance of the MPC990 makes the device ideal for Workstation,

Mainframe Computer and Telecommunication applications. The MPC990

offers an on–board crystal oscillator as the PLL reference and offers a

secondary single–ended ECL clock for system test capabilities.

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• Fully Integrated PLL

• Output Frequency Up to 400 MHz

• Operates from a 3.3 V Supply

• Output Frequency Configurable

• TQFP Packaging

LOW VOLTAGE

PLL CLOCK DRIVER

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50 ps Cycle–to–Cycle Jitter

The MPC990 offers three banks of outputs which can each be

programmed via the the four fsel pins of the device. There are 16 different

output frequency configurations available in the device. The configurations

include output ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and 4:3:2. The

programming table in this data sheet illustrates the various programming

options. The SYNC output monitors the relationship between the Qa and Qc

output banks. The output pulses per the timing diagrams in this data sheet

signal the coincident edges of the two output banks. This feature is useful

for non binary relationships between output frequencies (i.e., 3:2 or 4:3

relationships). The Sync_Sel input toggles the Qd outputs between sync

signals and extensions to the Qc bank of outputs.

FA SUFFIX

52–LEAD TQFP PACKAGE

CASE 848D–03

The MPC990 provides a separate output for the feedback to the PLL. This allows for the feedback frequency to be programmed

independently of the other outputs allowing for unique input vs output frequency relationships. The fselFB inputs provide 6 different

feedback frequencies from the QFB differential output pair. The MPC990 features an external feedback to the PLL.

The PLL_En, Ref_Sel and the Test_Clk input pins provide a means of bypassing the PLL and driving the output buffers directly.

This allows the user to single step a design during system debug. Note that the Test_Clk input is routed through the dividers so

that, depending on the programming, several edges on the Test_Clk input will be needed to get corresponding edge transitions on

the outputs. The VCO_Sel input provides a means of recentering the VCO to provide a broader range of VCO frequencies for

stable PLL operation.

If the frequency select or the VCO_Sel pins are changed during operation, a master reset signal must be applied to ensure

output synchronization and phase–lock. If the VCO is driven beyond its maximum frequency, the VCO can outrun the internal

dividers when the VCO_Sel pin is low. This will also prevent the PLL from achieving lock. Again, a master reset signal will need to

be applied to allow for phase–lock. The device employs a power–on reset circuit which will ensure output synchronization and PLL

lock on initial power–up.

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 Motorola, Inc. 2001

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与MPC990FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC991	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC991FAR2	MOTOROLA	获取价格	ECL SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, TQFP-
MPC992	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC992FA	NXP	获取价格	375MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32, LQFP-32
MPC992FA	MOTOROLA	获取价格	Clock Generator, 375MHz, CMOS, PQFP32, PLASTIC, TQFP-32
MPC992FA	IDT	获取价格	Clock Generator, 375MHz, PQFP32, LQFP-32
MPC993	MOTOROLA	获取价格	Dynamic Switch PLL Clock Driver
MPC993FA	NXP	获取价格	IC,1:5 OUTPUT, DIFFERENTIAL,CMOS,QFP,32PIN,PLASTIC
MPC993FA	MOTOROLA	获取价格	PLL Based Clock Driver, MPC900 Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PQFP3
MPC993FAR2	MOTOROLA	获取价格	MPC900 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLA

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