Datasheet > MPC9850VMR2

MPC9850VMR2

更新时间： 2024-11-12 19:49:15

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
12页	306K
描述
Processor Specific Clock Generator, 500MHz, CMOS, PBGA100, LEAD FREE, MAPBGA-100

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技术参数
数据手册
替代型号

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MPC9850VMR2 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LEAD FREE, MAPBGA-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.21
JESD-30 代码：	S-PBGA-B100	JESD-609代码：	e3
长度：	11 mm	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
最大输出时钟频率：	500 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA100,10X10,40
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	260	电源：	2.5/3.3,3.3 V
主时钟/晶体标称频率：	250 MHz	认证状态：	Not Qualified
座面最大高度：	1.7 mm	子类别：	Clock Generators
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	11 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

MPC9850VMR2 数据手册

Clock Generator for PowerQUICC III

MPC9850

Product Discontinuance Notice – Last Time Buy Expires on (1/31/2014)

DATASHEET

The MPC9850 is a PLL based clock generator specifically designed for

Freescale Microprocessor and Microcontroller applications including the

PowerQUICC III. This device generates a microprocessor input clock plus the

500 MHz Rapid I/O clock. The microprocessor clock is selectable in output

frequency to any of the commonly used microprocessor input and bus

frequencies. The Rapid I/O outputs are LVDS compatible. The device offers eight

low skew clock outputs organized into two output banks, each configurable to

support different clock frequencies. The extended temperature range of the

MPC9850 supports telecommunication and networking requirements.

MPC9850

MICROPROCESSOR

CLOCK GENERATOR

Features

•

8 LVCMOS outputs for processor and other circuitry

2 differential LVDS outputs for Rapid I/O interface

Crystal oscillator or external reference input

25 or 33 MHz Input reference frequency

Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,

50, 33 or 16 MHz

•

Buffered reference clock output

Rapid I/O (LVDS) Output = 500, 250 or 125 MHz

Low cycle-to-cycle and period jitter

VM SUFFIX (PB-FREE)

100 MAPBGA PACKAGE

CASE 1462-01

100-lead PBGA package, Pb-free

3.3V supply with 3.3V or 2.5V output LVCMOS drive

Supports computing, networking, telecommunications applications

Ambient temperature range –40°C to +85°C

Functional Description

The MPC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency

is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers,

divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111,

100, 83 66 50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use

in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency

is also divided to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III

communications processor. The input reference, either crystal or external input is also buffered to a separate output that my be

used as the clock source for a Gigabit Ethernet PHY if desired.

The reference clock may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a

25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and

selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal

oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are

required for crystal oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input

frequency.

The MPC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.

MPC9850 REVISION 6 FEBRUARY 6, 2013

12 3 4 5 6 7...12

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MPC9850VMR2 替代型号

型号	品牌	替代类型	描述	数据表
MPC9850VF	IDT	完全替代	Processor Specific Clock Generator, 500MHz, CMOS, PBGA100, MAPBGA-100
MPC9850VM	IDT	完全替代	Processor Specific Clock Generator, 500MHz, CMOS, PBGA100, LEAD FREE, MAPBGA-100

与MPC9850VMR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9855	MOTOROLA	获取价格	Clock Generator for PowerQUICC and PowerPC Microprocessors
MPC9855VF	IDT	获取价格	Processor Specific Clock Generator, 200MHz, PBGA100, MAPBGA-100
MPC9855VF	NXP	获取价格	200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, 11 X 11 MM, 1 MM PITCH, MAPBGA-100
MPC9855VF	MOTOROLA	获取价格	200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, MAPBGA-100
MPC9855VFR2	NXP	获取价格	200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, 11 X 11 MM, 1 MM PITCH, MAPBGA-100
MPC9855VM	NXP	获取价格	200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, MAPBGA-
MPC9855VMR2	IDT	获取价格	Processor Specific Clock Generator, 200MHz, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, MA
MPC9855VMR2	NXP	获取价格	200MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, MAPBGA-
MPC9857DW	NXP	获取价格	IC,1:10 OUTPUT, DIFFERENTIAL,CMOS,TSSOP,48PIN,PLASTIC
MPC9857DW	IDT	获取价格	PLL Based Clock Driver, 9857 Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, TSSO

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