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MPC9865VFR2 PDF预览

MPC9865VFR2

更新时间: 2024-11-12 18:53:59
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
12页 302K
描述
Clock Generator, PBGA100

MPC9865VFR2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92JESD-30 代码:S-PBGA-B100
JESD-609代码:e0端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA100,10X10,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
子类别:Clock Generators标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
Base Number Matches:1

MPC9865VFR2 数据手册

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DATA SHEET  
MPC9865  
Clock Generator for PowerQUICC III  
The MPC9865 is a PLL based clock generator specifically designed for  
Freescale Microprocessor and Microcontroller applications including the  
PowerPC and PowerQUICC. This device generates a microprocessor input  
clock. The microprocessor clock is selectable in output frequency to any of the  
commonly used microprocessor input and bus frequencies. The device offers  
eight low skew clock outputs in two banks, each configurable to support different  
clock frequencies. The extended temperature range of the MPC9865 supports  
telecommunication and networking requirements.  
MICROPROCESSOR  
CLOCK GENERATOR  
Features  
8 LVCMOS outputs for processor and other circuitry  
Crystal oscillator or external reference input  
25 or 33 MHz Input reference frequency  
Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66,  
50, 33, or 16 MHz  
VF SUFFIX  
VM SUFFIX (PB-FREE)  
100 MAPBGA PACKAGE  
CASE 1462-01  
Buffered reference clock output (2 copies)  
Low cycle-to-cycle and period jitter  
100-lead PBGA package  
100-lead Pb-free package available  
3.3 V supply with 3.3 V or 2.5 V LVCMOS output supplies  
Supports computing, networking, telecommunications applications  
Ambient temperature range –40°C to +85°C  
Functional Description  
The MPC9865 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency  
is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers,  
divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111,  
100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor  
or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also  
buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired.  
The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a  
25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and  
selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal  
oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are  
required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input  
frequency.  
The MPC9865 is packaged in a 100 lead MAPBGA package to optimize both performance and board density.  
IDT™ Clock Generator for PowerQUICC III  
MPC9865  
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc  
1

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