MPC930

更新时间： 2024-02-06 16:39:41

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器
页数	文件大小	规格书
14页	166K
描述
LOW VOLTAGE PLL CLOCK DRIVER

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MPC930 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	TQFP-32
针数：	32	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.26	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e0	长度：	7 mm
湿度敏感等级：	2	端子数量：	32
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	140 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	主时钟/晶体标称频率：	20 MHz
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
宽度：	7 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC

MPC930 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MPC930/931 is a 3.3V compatible, PLL based clock driver device

targeted for high performance clock applications. With output frequencies

of up to 150MHz and output skews of 300ps the MPC930/931 is ideal for

the most demanding clock distribution designs. The device employs a

fully differential PLL design to minimize cycle to cycle and long term jitter.

This parameter is of significant importance when the clock driver is

providing the reference clock for PLL’s on board todays microprocessors

and ASiC’s. The device offers 6 low skew outputs, and a choice between

internal or external feedback. The feedback option adds to the flexibility of

the device, providing numerous input to output frequency relationships.

LOW VOLTAGE

PLL CLOCK DRIVER

• On–Board Crystal Oscillator (MPC930)

• Differential LVPECL Reference Input (MPC931)

• Fully Integrated PLL

• Output Shut Down Mode

• Output Frequency up to 150MHz

• Compatible with PowerPC and Intel Microprocessors

• 32–Lead TQFP Packaging

• Power Down Mode

FA SUFFIX

32–LEAD TQFP PACKAGE

CASE 873A–02

• ±100ps Typical Cycle–to–Cycle Jitter

The MPC930 and MPC931 are very similar in basic functionality, but

there are some minor differences. The MPC931 has been optimized for

use as a zero delay buffer. In addition to tighter specification limits on the

phase offset of the device, a higher speed VCO has been used on the

MPC931. The MPC930, on the other hand, is more optimized for use as a

clock generator. When choosing between the 930 and 931, pay special

attention to the differences in the AC parameters of each device.

The MPC930/931 offers two power saving features for power conscious portable or “green” designs. The power down pin will

seemlessly reduce all of the clock rates by one half so that the system will run at half the potential clock rate to extend battery life.

The POWER_DN pin is synchronized internally to the slowest output clock rate. This allows the transition in and out of the

power–down mode to be output glitch free. In addition, the shut down control pins will turn off various combinations of clock

outputs while leaving a subset active to allow for total processor shut down while maintaining system monitors to “wake up” the

system when signaled. During shut down, the PLL will remain locked, if internal feedback is used, so that wake up time will be

minimized. The shut down and power down pins can be combined for the ultimate in power savings. The Shut_Dn pins are

synchronized to the clock internal to the chip to eliminate the possibility of generating runt pulses.

The MPC930/931 devices offer a great deal of flexibility in what is used as the PLL reference. The MPC930 offers an

integrated crystal oscillator that allows for an inexpensive crystal to be used as the frequency reference. For more information on

the crystal oscillator please refer to the applications section of this data sheet. In those applications where the 930/931 will be

used to regenerate clocks from an existing source or as a zero delay buffer, alternative reference clock inputs are provided. Both

devices offer an LVCMOS input that can be used as the PLL reference. In addition the MPC931 replaces the crystal oscillator

inputs with a differential PECL reference clock input that allows the device to be used in mixed technology clock distribution trees.

An internal feedback divide by 8 of the VCO frequency is compared with the input reference provided by the on–board crystal

oscillator when the internal feedback is selected. The on–board crystal oscillator requires no external components other than a

series resonant crystal (see Applications Information section for more on crystals). The internal VCO is running at 8x the input

reference clock. The outputs can be configured to run at 4x, 2x, 1.25x or 0.66x the input reference frequency. If the external

feedback is selected, one of the MPC931’s outputs must be connected to the Ext_FB pin. Using the external feedback, numerous

input/output frequency relationships can be developed.

The MPC930/931 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS

or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50Ω transmission

lines. For series terminated applications, each output can drive two 50Ω transmission lines, effectively increasing the fanout to

1:12. The device is packaged in a 32–lead TQFP package to provide the optimum combination of board density and cost.

PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.

1/97

REV 3

Motorola, Inc. 1997

12 3 4 5 6 7...14

中文翻译

下载PDF

与MPC930相关器件

型号	品牌	获取价格	描述	数据表
MPC930FA	MOTOROLA	获取价格	Processor Specific Clock Generator, 140MHz, CMOS, PQFP32, PLASTIC, TQFP-32
MPC930FAR2	MOTOROLA	获取价格	140MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32, TQFP-32
MPC931	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC9315	MOTOROLA	获取价格	2.5V and 3.3V CMOS PLL Clock Generator and Driver
MPC9315	IDT	获取价格	PLL Based Clock Driver
MPC9315AC	NXP	获取价格	9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9315FA	NXP	获取价格	9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9315FA	MOTOROLA	获取价格	2.5V and 3.3V CMOS PLL Clock Generator and Driver
MPC9315FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32
MPC9315FAR2	NXP	获取价格	9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7

与MPC930相关文章

压敏电阻与气体放电管串联使用的专业解析
2024-07-01

8
手册解读：MMBT3904参数与管脚图及代换
2024-07-01

5
74LS298PC手册解读：参数说明、引脚说明、替代型号推荐
2024-07-01

3
L6234手册解读：引脚信息、电气参数
2024-07-01

4

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC930

MPC930 技术参数

MPC930 数据手册

与MPC930相关器件

与MPC930相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC930

MPC930 技术参数

MPC930 数据手册

与MPC930相关器件

与MPC930相关文章

您还可以找

您在本页遇到什么问题？