Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9259/D
Rev 0, 12/2002
The MPC9259 is a 3.3V compatible, PLL based clock synthesizer
targeted for high performance clock generation in mid-range to
high-performance telecom, networking and computing applications. With
output frequencies from 50 MHz to 900 MHz and the support of differential
LVDS output signals the device meets the needs of the most demanding
clock applications.
900 MHZ LOW VOLTAGE
CLOCK SYNTHESIZER
Features
• 50 MHz to 900 MHz synthesized clock output signal
• Differential LVDS output
• LVCMOS compatible control inputs
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS compatible reference input
• 3.3V power supply
• Fully integrated PLL
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
• Minimal frequency overshoot
• Serial 3-wire programming interface
• Parallel programming interface for power-up
• 32 Pin LQFP Package
• SiGe Technology
• Ambient temperature range 0°C to + 70° C
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range
of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal
oscillator frequency f , the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
XTAL
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock.
The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be
programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this
document. The configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input.
See the programming section for more information. The TEST output reflects various internal node values, and is controlled by
the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST
output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked
by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the
PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
For More Information On This Product,
Motorola, Inc. 2002
Go to: www.freescale.com
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