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MCM63D836VF100 PDF预览

MCM63D836VF100

更新时间： 2024-11-11 20:45:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 静态存储器内存集成电路
页数 文件大小 规格书
18页 355K
描述
Multi-Port SRAM, 256KX36, 5ns, CMOS, PBGA209

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中文翻译

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MCM63D836VF100 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：BGA, BGA209,11X19,40Reach Compliance Code：unknown
风险等级：5.92最长访问时间：5 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B209
JESD-609代码：e0内存密度：9437184 bit
内存集成电路类型：MULTI-PORT SRAM内存宽度：36
端口数量：2端子数量：209
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA209,11X19,40
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL电源：3.3 V
认证状态：Not Qualified最大待机电流：0.1 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.35 mA标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMBase Number Matches：1

MCM63D836VF100 数据手册

 浏览型号MCM63D836VF100的Datasheet PDF文件第2页浏览型号MCM63D836VF100的Datasheet PDF文件第3页浏览型号MCM63D836VF100的Datasheet PDF文件第4页浏览型号MCM63D836VF100的Datasheet PDF文件第5页浏览型号MCM63D836VF100的Datasheet PDF文件第6页浏览型号MCM63D836VF100的Datasheet PDF文件第7页 
Order Number: MCM63D836/D  
Rev. 0, 8/10/00  
MOTOROLA  
Semiconductor Products Sector  
MCM63D836  
MCM64D836  
Product Preview  
256K x 36 Bit Synchronous  
Dual I/O, Dual Address SRAM  
The MCM63D836 and MCM64D836 are 8M-bit static random access  
memories, organized as 256K words of 36 bits. They feature common data  
input and data output buffers and incorporate input and output registers on-  
board with high speed SRAM.  
The MCM63D836 and MCM64D836 allow the user to concurrently perform  
reads or writes in combination on the two data ports. The two address ports  
(AX, AY) determine the read or write locations for their respective data ports  
(DQX, DQY).  
The synchronous design allows for precise cycle control with the use of an  
external single clock (K). All signal pins except output enables (GX, GY) are  
registered on the rising edge of clock (K).  
For the case when AX and AY are the same, certain protocols are followed.  
If both ports are read, the reads occur normally. If one port is written and the  
other is read, the read from the array will occur before the data is written. If  
both ports are written, only the data on DQY will be written to the array.  
VF PACKAGE  
209-BUMP MAPBGA  
T
CASE 1170A-01  
F
A
E
C
I
R
T
D
O
N
N
T
The MCM63D836 operates on a single 3.3 V power supply. The  
MCM64D836 operates on a single 2.5 V power supply.  
U
O
O
I
H
• MCM63D836-100: 5 ns Access/10 ns Cycle (100 MHz), 3.3 V Device  
T
0
I
MCM64D836-100: 5 ns Access/10 ns Cycle (100 MHz), 2.A5 V DTeviceW  
0
/
• Single 3.3 V ±5% or 2.5 V ±200 mV Power Supply  
0
1
• Single Clock Operation  
• Self-Timed Write  
• Two Bi-Directional Data Buses  
• Asynchronous Output Enables (GX, GY)  
• LVTTL Compatible I/O  
E
/
C
8
G
I
N
N
L
A
O
I
H
B
S
C
I
• Concurrent Reads and Writes  
• Full Byte Write Control  
V
U
O
E
T
• Dual Cycle Deselect FunctionaliPty  
R
T
-
• Compatible with IEEE 1149.1 Test Access Port (JTAG)  
C
E
S
• 209-Bump, 1 mm Pitch, 14 x 22 mmEMAPBGA Package  
J
R
B
Suggested Applications  
—ATM  
—Cell/Frame Buffers  
U
— Ethernet Switches — Routers  
— Cellular Base Stations  
— Shared Memory — RAID Systems  
P
— SNA Switches  
This document contains information on a new product under development.  
Motorola reserves the right to change or discontinue this product without notice.  
© Motorola, Inc., 2000. All rights reserved.  
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