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MCM63F733ATQ10R PDF预览

MCM63F733ATQ10R

更新时间: 2024-10-01 22:05:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器
页数 文件大小 规格书
16页 238K
描述
128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

MCM63F733ATQ10R 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.65
Is Samacsys:N最长访问时间:10 ns
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:4194304 bit
内存集成电路类型:CACHE SRAM内存宽度:32
功能数量:1端口数量:1
端子数量:100字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX32输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

MCM63F733ATQ10R 数据手册

 浏览型号MCM63F733ATQ10R的Datasheet PDF文件第2页浏览型号MCM63F733ATQ10R的Datasheet PDF文件第3页浏览型号MCM63F733ATQ10R的Datasheet PDF文件第4页浏览型号MCM63F733ATQ10R的Datasheet PDF文件第5页浏览型号MCM63F733ATQ10R的Datasheet PDF文件第6页浏览型号MCM63F733ATQ10R的Datasheet PDF文件第7页 
Order this document  
by MCM63F733A/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM63F733A  
Advance Information  
128K x 32 Bit Flow–Through  
BurstRAM Synchronous  
Fast Static RAM  
The MCM63F733A is a 4M–bit synchronous fast static RAM designed to pro-  
vide a burstable, high performance, secondary cache for the PowerPC and  
other high performance microprocessors. It is organized as 128K words of 32  
bits each, fabricated with high performance silicon gate CMOS technology.  
This device integrates input registers, a 2–bit address counter, and high speed  
SRAM onto a single monolithic circuit for reduced parts count in cache data  
RAM applications. Synchronous design allows precise cycle control with the  
use of an external clock (K). CMOS circuitry reduces the overall power con-  
sumption of the integrated functions for greater reliability.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
Addresses (SA), data inputs (DQx), and all control signals except output  
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through  
positive–edge–triggered noninverting registers.  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM63F733A (burst sequence  
operates in linear or interleaved mode dependent upon state of LBO) and con-  
trolled by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable (SW) are provided to allow writes to either individual bytes or  
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls  
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte  
writes SBx are asserted with SW. All bytes are written if either SGW is asserted  
or if all SBx and SW are asserted.  
For read cycles, a flow–through SRAM allows output data to simply flow freely  
from the memory array.  
The MCM63F733A operates from a 3.3 V core power supply and all outputs  
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC  
Standard JESD8–5 compatible.  
MCM63F733A–10 = 10 ns Access/13 ns Cycle (75 MHz)  
MCM63F733A–11 = 11 ns Access/15 ns Cycle (66 MHz)  
3.3 V + 10%/– 5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
Single–Cycle Deselect  
Sleep Mode (ZZ)  
100–Pin TQFP Package  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 2  
3/20/98  
Motorola, Inc. 1998  

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