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MC145201DT PDF预览

MC145201DT

更新时间: 2024-01-11 20:45:09
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飞思卡尔 - FREESCALE 光电二极管
页数 文件大小 规格书
23页 334K
描述
2.0 GHz PLL Frequency Synthesizers

MC145201DT 数据手册

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Order this document  
by MC145200/D  
SEMICONDUCTOR TECHNICAL DATA  
Include On–Board 64/65 Prescalers  
The MC145200 and MC145201 are single–package synthesizers with serial  
interfaces capable of direct usage up to 2.0 GHz. A special architecture makes  
these PLLs very easy to program because a byte–oriented format is utilized.  
Due to the patented BitGrabber registers, no address/steering bits are  
required for random access of the three registers. Thus, tuning can be  
accomplished via a 3–byte serial transfer to the 24–bit A register. The interface  
is both SPI and MICROWIRE compatible.  
Each device features a single–ended current source/sink phase detector  
output and a double–ended phase detector output. Both phase detectors have  
linear transfer functions (no dead zones). The maximum current of the  
single–ended phase detector output is determined by an external resistor tied  
from the Rx pin to ground. This current can be varied via the serial port.  
The MC145200 features logic–level converters and high–voltage phase/  
frequency detectors; the detector supply may range up to 9.5 V. The MC145201  
has lower–voltage phase/frequency detectors optimized for single–supply  
systems of 5 V ±10%.  
F SUFFIX  
SOG PACKAGE  
CASE 751J  
20  
1
DT SUFFIX  
TSSOP  
CASE 948D  
20  
1
ORDERING INFORMATION  
MC145200F  
MC145201F  
SOG Package  
SOG Package  
MC145200DT TSSOP  
MC145201DT TSSOP  
Each part includes a differential RF input which may be operated in a  
single–ended mode. Also featured are on–board support of an external crystal  
and a programmable reference output. The R, A, and N counters are fully  
programmable. The C register (configuration register) allows the parts to be  
configured to meet various applications. A patented feature allows the C  
register to shut off unused outputs, thereby minimizing system noise and  
interference.  
In order to have consistent lock times and prevent erroneous data from being  
loaded into the counters, on–board circuitry synchronizes the update of the A  
register if the A or N counters are loading. Similarly, an update of the R register  
is synchronized if the R counter is loading.  
PIN ASSIGNMENT  
REF  
1
2
3
20  
19  
18  
REF  
in  
out  
LD  
D
in  
CLK  
φ
R
φ
V
4
5
6
17  
16  
15  
ENB  
OUTPUT A  
OUTPUT B  
V
PD  
PD  
The double–buffered R register allows new divide ratios to be presented to  
the three counters (R, A, and N) simultaneously.  
out  
GND  
Rx  
V
7
14  
13  
12  
11  
DD  
Maximum Operating Frequency: 2000 MHz @ V = 200 mV p–p  
in  
8
TEST 2  
Operating Supply Current: 12 mA Nominal  
TEST 1  
9
Operating Supply Voltage Range (V  
Operating Supply Voltage Range of Phase Detectors (V  
MC145200: 8.0 to 9.5 V  
and V  
Pins): 4.5 to 5.5 V  
V
f
DD  
CC  
CC  
Pin) —  
PD  
10  
f
in  
in  
MC145201: 4.5 to 5.5 V  
Current Source/Sink Phase Detector Output Capability: 2 mA Maximum  
Gain of Current Source/Sink Phase/Frequency Detector Controllable via  
Serial Port  
Operating Temperature Range: – 40 to +85°C  
R Counter Division Range: (1 and) 5 to 8191  
Dual–Modulus Capability Provides Total Division up to 262,143  
High–Speed Serial Interface: 4 Mbps  
OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices  
Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)  
OUTPUT B: Open–Drain  
Power–Saving Standby Feature with Orderly Recovery for Minimizing Lock  
Times, Standby Current: 30 µA  
Evaluation Kit Available (Part Numbers MC145200EVK and MC145201EVK)  
See Application Note AN1253/D for Low–Pass Filter Design, and  
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping  
BitGrabber is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.  
REV 4  
1/98  
TN98012300  
Motorola, Inc. 1998  

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Evaluation Board Manual