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MC14520BDW PDF预览

MC14520BDW

更新时间: 2024-09-09 04:59:27
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管
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描述
Dual Up Counters

MC14520BDW 数据手册

 浏览型号MC14520BDW的Datasheet PDF文件第2页浏览型号MC14520BDW的Datasheet PDF文件第3页浏览型号MC14520BDW的Datasheet PDF文件第4页浏览型号MC14520BDW的Datasheet PDF文件第5页浏览型号MC14520BDW的Datasheet PDF文件第6页浏览型号MC14520BDW的Datasheet PDF文件第7页 
MC14518B, MC14520B  
Dual Up Counters  
The MC14518B dual BCD counter and the MC14520B dual binary  
counter are constructed with MOS P−channel and N−channel  
enhancement mode devices in a single monolithic structure. Each  
consists of two identical, independent, internally synchronous 4−stage  
counters. The counter stages are type D flip−flops, with interchangeable  
Clock and Enable lines for incrementing on either the positive−going or  
negative−going transition as required when cascading multiple stages.  
Each counter can be cleared by applying a high level on the Reset line.  
In addition, the MC14518B will count out of all undefined states within  
two clock periods. These complementary MOS up counters find  
primary use in multi−stage synchronous or ripple counting applications  
requiring low power dissipation and/or high noise immunity.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP−16  
P SUFFIX  
CASE 648  
MC145xxBCP  
AWLYYWWG  
Features  
1
Diode Protection on All Inputs  
16  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Internally Synchronous for High Internal and External Speeds  
SOIC−16  
DW SUFFIX  
CASE 751G  
145xxB  
AWLYYWWG  
Logic Edge−Clocked Design — Incremented on Positive Transition  
of Clock or Negative Transition on Enable  
Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load Over the Rated Temperature Range  
Pb−Free Packages are Available*  
1
16  
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC145xxB  
ALYWG  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 1.)  
SS  
Symbol  
Parameter  
Value  
Unit  
V
1
V
DD  
DC Supply Voltage Range  
0.5 to +18.0  
xx  
= 18 or 20  
V , V  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
in out  
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
WW, W = Work Week  
G
= Pb−Free Indicator  
P
D
Power Dissipation,  
500  
mW  
per Package (Note 2.)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
T
Operating Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
A
T
stg  
T
Lead Temperature  
L
(8−Second Soldering)  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Maximum Ratings are those values beyond which damage to the device  
may occur.  
2. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
January, 2006 − Rev. 5  
MC14518B/D  
 

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