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MC145202DT1

更新时间： 2024-11-18 20:44:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 输入元件光电二极管
页数 文件大小 规格书
4页 111K
描述
PLL Frequency Synthesizer, PDSO20, PLASTIC, TSSOP-20

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中文翻译

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MC145202DT1 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.7其他特性：6-BIT AUXILIARY INPUT COUNTER; SELECTABLE 64/65 PRESCALER
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：R-PDSO-G20
长度：6.5 mm功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

MC145202DT1 数据手册

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Order this document by MC145202–1PP/D  
The MC145202–1 is pin–for–pin compatible with the previous generation  
MC145200, MC145201, and MC145202. Table 1 highlights the different  
features in these four devices. The MC145202–1 is recommended for new  
designs, and also offers improved suppression of reference sideband spurs.  
The counters are programmed via a synchronous serial port which is SPI  
compatible. The serial port is byte-oriented to facilitate control via an MCU.  
Due to the innovative BitGrabber Plus registers, the MC145202–1 may be  
cascaded with other peripherals featuring BitGrabber Plus without requiring  
leading dummy bits or address bits in the serial data stream. In addition,  
BitGrabber Plus peripherals may be cascaded with existing BitGrabber  
peripherals.  
The device features a single–ended current source/sink phase detector A  
output and a double–ended phase detector B output. Both phase detectors  
have linear transfer functions (no dead zones). The maximum current of the  
single–ended phase detector output is determined by an external resistor  
tied from the Rx pin to ground. This current can be varied via the serial port.  
PLL FREQUENCY  
SYNTHESIZER  
SEMICONDUCTOR  
TECHNICAL DATA  
F SUFFIX  
PLASTIC PACKAGE  
CASE 751J  
20  
1
(SO–20)  
Slew–rate control is provided by a special driver designed for the REF  
out  
pin. This minimizes interference caused by REF  
.
out  
This part includes a differential RF input that may be operated in a  
single–ended mode. Also featured are on–board support of an external  
crystal and a programmable reference output. The R, A, and N counters are  
fully programmable. The C register (configuration register) allows the part to  
be configured to meet various applications. A patented feature allows the C  
register to shut off unused outputs, thereby minimizing system noise and  
interference.  
DT SUFFIX  
PLASTIC PACKAGE  
CASE 948D  
20  
1
(TSSOP–20)  
In order to have consistent lock times and prevent erroneous data from  
being loaded into the counters, on–board circuitry synchronizes the update  
of the A register if the A or N counters are loading. Similarly, an update of the  
R register is synchronized if the R counter is loading.  
The double–buffered R register allows new divide ratios to be presented  
to the three counters (R, A, and N) simultaneously.  
PIN CONNECTIONS  
REF  
1
2
20  
19  
REF  
in  
out  
LD  
D
in  
φ
3
18 CLK  
17 ENB  
16  
R
4
φ
V
• Maximum Operating Frequency: 2000 MHz @ –10 dBm  
• Operating Supply Current: 4 mA Nominal at 3.0 V  
V
PD  
5
Output A  
15  
14  
6
PD  
Output B  
out  
Gnd  
Rx  
• Operating Supply Voltage Range (V , V , V  
Pins): 2.7 to 5.5 V  
DD CC PD  
7
V
DD  
• Current Source/Sink Phase Detector Output:  
8
13 Test 2  
1.7 mA @ 5.0 V or 1.0 mA @ 3.0 V  
9
12  
11  
V
CC  
Test 1  
• Gain of Current Source/Sink Phase/Frequency Detector Controllable via  
f
in  
10  
f
in  
Serial Port  
• R Counter Division Range: 1 and 5 to 8191  
• Dual–Modulus Capability Provides Total Division up to 262,143  
• High–Speed Serial Interface: 4 Mbps  
(Top View)  
EVALUATION KIT  
• Output A Pin, When Configured as Data Out, Permits Cascading of  
Devices  
The P/N TBD, which contains hardware and  
software, will be available.  
• Two General–Purpose Digital Outputs:  
Output A: Totem–Pole (Push–Pull) with Four Output Modes  
Output B: Open–Drain  
ORDERING INFORMATION  
Operating  
• Patented Power–Saving Standby Feature with Orderly Recovery for  
Minimizing Lock Times, Standby Current: 30 µA  
Temperature Range  
Device  
Package  
• See App Note AN1253/D for Low–Pass Filter Design, and AN1277/D for  
Offset Reference PLLs for Fine Resolution or Fast Hopping  
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.  
MC145202F1  
MC145202DT1  
SO–20  
T
A
= –40 to 85°C  
TSSOP–20  
This document contains information on a product under development. Motorola reserves the  
Motorola, Inc. 1999  
Rev 0  
right to change or discontinue this product without notice.  
1234

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